fda9aaa60e
All Aspeed SoC clocks are driven by an input source clock which can have different frequencies : 24MHz or 25MHz, and also, on the Aspeed AST2400 SoC, 48MHz. The H-PLL (CPU) clock is defined from a calculation using parameters in the H-PLL Parameter register or from a predefined set of frequencies if the setting is strapped by hardware (Aspeed AST2400 SoC). The other clocks of the SoC are then defined from the H-PLL using dividers. We introduce first the APB clock because it should be used to drive the Aspeed timer model. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 20180622075700.5923-2-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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| .. | ||
| macio | ||
| a9scu.h | ||
| arm11scu.h | ||
| arm_integrator_debug.h | ||
| aspeed_scu.h | ||
| aspeed_sdmc.h | ||
| auxbus.h | ||
| bcm2835_mbox.h | ||
| bcm2835_mbox_defs.h | ||
| bcm2835_property.h | ||
| bcm2835_rng.h | ||
| imx2_wdt.h | ||
| imx6_ccm.h | ||
| imx6_src.h | ||
| imx7_ccm.h | ||
| imx7_gpr.h | ||
| imx7_snvs.h | ||
| imx25_ccm.h | ||
| imx31_ccm.h | ||
| imx_ccm.h | ||
| iotkit-secctl.h | ||
| ivshmem.h | ||
| mips_cmgcr.h | ||
| mips_cpc.h | ||
| mips_itu.h | ||
| mmio_interface.h | ||
| mos6522.h | ||
| mps2-fpgaio.h | ||
| mps2-scc.h | ||
| msf2-sysreg.h | ||
| pca9552.h | ||
| pca9552_regs.h | ||
| pvpanic.h | ||
| stm32f2xx_syscfg.h | ||
| tmp105_regs.h | ||
| tz-mpc.h | ||
| tz-ppc.h | ||
| unimp.h | ||
| vmcoreinfo.h | ||
| zynq-xadc.h | ||