fdad6ec30d
The has_otp attribute is enabled in the SBC subclasses for AST1030 to control the presence of OTP support per SoC type. Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250812094011.2617526-7-kane_chen@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
51 lines
1.2 KiB
C
51 lines
1.2 KiB
C
/*
|
|
* ASPEED Secure Boot Controller
|
|
*
|
|
* Copyright (C) 2021-2022 IBM Corp.
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0-or-later
|
|
*/
|
|
|
|
#ifndef ASPEED_SBC_H
|
|
#define ASPEED_SBC_H
|
|
|
|
#include "hw/sysbus.h"
|
|
#include "hw/nvram/aspeed_otp.h"
|
|
|
|
#define TYPE_ASPEED_SBC "aspeed.sbc"
|
|
#define TYPE_ASPEED_AST2600_SBC TYPE_ASPEED_SBC "-ast2600"
|
|
#define TYPE_ASPEED_AST10X0_SBC TYPE_ASPEED_SBC "-ast10x0"
|
|
OBJECT_DECLARE_TYPE(AspeedSBCState, AspeedSBCClass, ASPEED_SBC)
|
|
|
|
#define ASPEED_SBC_NR_REGS (0x93c >> 2)
|
|
|
|
#define QSR_AES BIT(27)
|
|
#define QSR_RSA1024 (0x0 << 12)
|
|
#define QSR_RSA2048 (0x1 << 12)
|
|
#define QSR_RSA3072 (0x2 << 12)
|
|
#define QSR_RSA4096 (0x3 << 12)
|
|
#define QSR_SHA224 (0x0 << 10)
|
|
#define QSR_SHA256 (0x1 << 10)
|
|
#define QSR_SHA384 (0x2 << 10)
|
|
#define QSR_SHA512 (0x3 << 10)
|
|
|
|
struct AspeedSBCState {
|
|
SysBusDevice parent;
|
|
|
|
bool emmc_abr;
|
|
uint32_t signing_settings;
|
|
|
|
MemoryRegion iomem;
|
|
|
|
uint32_t regs[ASPEED_SBC_NR_REGS];
|
|
|
|
AspeedOTPState otp;
|
|
};
|
|
|
|
struct AspeedSBCClass {
|
|
SysBusDeviceClass parent_class;
|
|
|
|
bool has_otp;
|
|
};
|
|
|
|
#endif /* ASPEED_SBC_H */
|