f95b970275
With function get_physical_address(), parameter MMUContext is added and remove parameter address, prot and address. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
264 lines
8 KiB
C
264 lines
8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* LoongArch CPU helpers for qemu
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*
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* Copyright (c) 2024 Loongson Technology Corporation Limited
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*
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*/
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#include "qemu/osdep.h"
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#include "system/tcg.h"
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#include "cpu.h"
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#include "accel/tcg/cpu-mmu-index.h"
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#include "exec/target_page.h"
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#include "internals.h"
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#include "cpu-csr.h"
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#include "cpu-mmu.h"
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#include "tcg/tcg_loongarch.h"
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void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
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uint64_t *dir_width, target_ulong level)
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{
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switch (level) {
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case 1:
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*dir_base = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, DIR1_BASE);
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*dir_width = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, DIR1_WIDTH);
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break;
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case 2:
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*dir_base = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, DIR2_BASE);
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*dir_width = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, DIR2_WIDTH);
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break;
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case 3:
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*dir_base = FIELD_EX64(env->CSR_PWCH, CSR_PWCH, DIR3_BASE);
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*dir_width = FIELD_EX64(env->CSR_PWCH, CSR_PWCH, DIR3_WIDTH);
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break;
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case 4:
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*dir_base = FIELD_EX64(env->CSR_PWCH, CSR_PWCH, DIR4_BASE);
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*dir_width = FIELD_EX64(env->CSR_PWCH, CSR_PWCH, DIR4_WIDTH);
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break;
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default:
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/* level may be zero for ldpte */
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*dir_base = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTBASE);
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*dir_width = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTWIDTH);
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break;
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}
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}
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TLBRet loongarch_check_pte(CPULoongArchState *env, MMUContext *context,
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MMUAccessType access_type, int mmu_idx)
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{
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uint64_t plv = mmu_idx;
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uint64_t tlb_entry, tlb_ppn;
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uint8_t tlb_ps, tlb_v, tlb_d, tlb_plv, tlb_nx, tlb_nr, tlb_rplv;
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tlb_entry = context->pte;
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tlb_ps = context->ps;
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tlb_v = FIELD_EX64(tlb_entry, TLBENTRY, V);
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tlb_d = FIELD_EX64(tlb_entry, TLBENTRY, D);
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tlb_plv = FIELD_EX64(tlb_entry, TLBENTRY, PLV);
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if (is_la64(env)) {
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tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_64, PPN);
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tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY_64, NX);
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tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY_64, NR);
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tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY_64, RPLV);
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} else {
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tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_32, PPN);
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tlb_nx = 0;
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tlb_nr = 0;
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tlb_rplv = 0;
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}
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/* Remove sw bit between bit12 -- bit PS*/
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tlb_ppn = tlb_ppn & ~(((0x1UL << (tlb_ps - 12)) - 1));
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/* Check access rights */
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if (!tlb_v) {
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return TLBRET_INVALID;
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}
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if (access_type == MMU_INST_FETCH && tlb_nx) {
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return TLBRET_XI;
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}
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if (access_type == MMU_DATA_LOAD && tlb_nr) {
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return TLBRET_RI;
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}
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if (((tlb_rplv == 0) && (plv > tlb_plv)) ||
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((tlb_rplv == 1) && (plv != tlb_plv))) {
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return TLBRET_PE;
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}
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if ((access_type == MMU_DATA_STORE) && !tlb_d) {
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return TLBRET_DIRTY;
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}
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context->physical = (tlb_ppn << R_TLBENTRY_64_PPN_SHIFT) |
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(context->addr & MAKE_64BIT_MASK(0, tlb_ps));
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context->prot = PAGE_READ;
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if (tlb_d) {
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context->prot |= PAGE_WRITE;
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}
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if (!tlb_nx) {
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context->prot |= PAGE_EXEC;
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}
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return TLBRET_MATCH;
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}
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static TLBRet loongarch_page_table_walker(CPULoongArchState *env,
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MMUContext *context,
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int access_type, int mmu_idx)
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{
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CPUState *cs = env_cpu(env);
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target_ulong index, phys;
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uint64_t dir_base, dir_width;
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uint64_t base;
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int level;
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vaddr address;
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address = context->addr;
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if ((address >> 63) & 0x1) {
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base = env->CSR_PGDH;
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} else {
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base = env->CSR_PGDL;
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}
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base &= TARGET_PHYS_MASK;
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for (level = 4; level > 0; level--) {
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get_dir_base_width(env, &dir_base, &dir_width, level);
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if (dir_width == 0) {
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continue;
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}
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/* get next level page directory */
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index = (address >> dir_base) & ((1 << dir_width) - 1);
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phys = base | index << 3;
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base = ldq_phys(cs->as, phys) & TARGET_PHYS_MASK;
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if (FIELD_EX64(base, TLBENTRY, HUGE)) {
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/* base is a huge pte */
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break;
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}
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}
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/* pte */
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if (FIELD_EX64(base, TLBENTRY, HUGE)) {
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/* Huge Page. base is pte */
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base = FIELD_DP64(base, TLBENTRY, LEVEL, 0);
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base = FIELD_DP64(base, TLBENTRY, HUGE, 0);
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if (FIELD_EX64(base, TLBENTRY, HGLOBAL)) {
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base = FIELD_DP64(base, TLBENTRY, HGLOBAL, 0);
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base = FIELD_DP64(base, TLBENTRY, G, 1);
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}
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} else {
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/* Normal Page. base points to pte */
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get_dir_base_width(env, &dir_base, &dir_width, 0);
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index = (address >> dir_base) & ((1 << dir_width) - 1);
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phys = base | index << 3;
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base = ldq_phys(cs->as, phys);
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}
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context->ps = dir_base;
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context->pte = base;
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return loongarch_check_pte(env, context, access_type, mmu_idx);
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}
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static TLBRet loongarch_map_address(CPULoongArchState *env,
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MMUContext *context,
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MMUAccessType access_type, int mmu_idx,
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int is_debug)
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{
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TLBRet ret;
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if (tcg_enabled()) {
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ret = loongarch_get_addr_from_tlb(env, context, access_type, mmu_idx);
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if (ret != TLBRET_NOMATCH) {
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return ret;
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}
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}
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if (is_debug) {
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/*
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* For debugger memory access, we want to do the map when there is a
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* legal mapping, even if the mapping is not yet in TLB. return 0 if
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* there is a valid map, else none zero.
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*/
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return loongarch_page_table_walker(env, context, access_type, mmu_idx);
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}
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return TLBRET_NOMATCH;
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}
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static hwaddr dmw_va2pa(CPULoongArchState *env, vaddr va, target_ulong dmw)
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{
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if (is_la64(env)) {
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return va & TARGET_VIRT_MASK;
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} else {
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uint32_t pseg = FIELD_EX32(dmw, CSR_DMW_32, PSEG);
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return (va & MAKE_64BIT_MASK(0, R_CSR_DMW_32_VSEG_SHIFT)) | \
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(pseg << R_CSR_DMW_32_VSEG_SHIFT);
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}
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}
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TLBRet get_physical_address(CPULoongArchState *env, MMUContext *context,
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MMUAccessType access_type, int mmu_idx,
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int is_debug)
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{
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int user_mode = mmu_idx == MMU_USER_IDX;
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int kernel_mode = mmu_idx == MMU_KERNEL_IDX;
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uint32_t plv, base_c, base_v;
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int64_t addr_high;
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uint8_t da = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, DA);
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uint8_t pg = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG);
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vaddr address;
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/* Check PG and DA */
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address = context->addr;
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if (da & !pg) {
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context->physical = address & TARGET_PHYS_MASK;
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context->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return TLBRET_MATCH;
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}
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plv = kernel_mode | (user_mode << R_CSR_DMW_PLV3_SHIFT);
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if (is_la64(env)) {
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base_v = address >> R_CSR_DMW_64_VSEG_SHIFT;
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} else {
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base_v = address >> R_CSR_DMW_32_VSEG_SHIFT;
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}
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/* Check direct map window */
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for (int i = 0; i < 4; i++) {
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if (is_la64(env)) {
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base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW_64, VSEG);
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} else {
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base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW_32, VSEG);
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}
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if ((plv & env->CSR_DMW[i]) && (base_c == base_v)) {
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context->physical = dmw_va2pa(env, address, env->CSR_DMW[i]);
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context->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return TLBRET_MATCH;
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}
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}
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/* Check valid extension */
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addr_high = (int64_t)address >> (TARGET_VIRT_ADDR_SPACE_BITS - 1);
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if (!(addr_high == 0 || addr_high == -1ULL)) {
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return TLBRET_BADADDR;
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}
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/* Mapped address */
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return loongarch_map_address(env, context, access_type, mmu_idx, is_debug);
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}
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hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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{
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CPULoongArchState *env = cpu_env(cs);
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MMUContext context;
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context.addr = addr;
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if (get_physical_address(env, &context, MMU_DATA_LOAD,
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cpu_mmu_index(cs, false), 1) != TLBRET_MATCH) {
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return -1;
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}
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return context.physical;
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}
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