Richard Henderson 55b490b58f target/riscv: Record misa_ext in TCGTBCPUState.cs_base ... The tb_flush within write_misa was incorrect. It assumed that we could adjust the ISA of the current processor and discard all TB and all would be well. But MISA is per vcpu, so globally flushing TB does not mean that the TB matches the MISA of any given vcpu. By recording misa in the tb state, we ensure that the code generated matches the vcpu. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>		2025-09-24 10:29:43 -07:00
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meson.build
tcg-cpu.c	target/riscv: Record misa_ext in TCGTBCPUState.cs_base	2025-09-24 10:29:43 -07:00
tcg-cpu.h	target/riscv: Remove AccelCPUClass::cpu_class_init need	2025-04-23 15:07:32 -07:00