qemu-cr16/target
Frank Chang 3dd2168c33 target/riscv: Add Zc extension implied rule
Zc extension has special implied rules that need to be handled separately.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
Tested-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240625114629.27793-6-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26 23:12:21 +10:00
..
alpha
arm gdbstub: move enums into separate header 2024-06-24 10:14:17 +01:00
avr
cris
hexagon target/hexagon: idef-parser simplify predicate init 2024-06-08 17:49:36 -07:00
hppa
i386 gdbstub: move enums into separate header 2024-06-24 10:14:17 +01:00
loongarch target/loongarch: fix a wrong print in cpu dump 2024-06-06 11:58:06 +08:00
m68k
microblaze
mips target/mips: Remove unused 'hw/misc/mips_itu.h' header 2024-06-04 10:02:39 +02:00
openrisc
ppc gdbstub: move enums into separate header 2024-06-24 10:14:17 +01:00
riscv target/riscv: Add Zc extension implied rule 2024-06-26 23:12:21 +10:00
rx
s390x maintainer updates (plugins, gdbstub): 2024-06-24 13:51:11 -07:00
sh4
sparc target/sparc: use signed denominator in sdiv helper 2024-06-19 13:50:22 -07:00
tricore
xtensa
Kconfig
meson.build