qemu-cr16/target
Peter Maydell a530e470ea target/arm: Permit T32 LDM with single register
For the Thumb T32 encoding of LDM, if only a single register is
specified in the register list this instruction is UNPREDICTABLE,
with the following choices:
 * instruction UNDEFs
 * instruction is a NOP
 * instruction loads a single register
 * instruction loads an unspecified set of registers

Currently we choose to UNDEF (a behaviour chosen in commit
4b222545db in 2019; previously we treated it as "load the
specified single register").

Unfortunately there is real world code out there (which shipped in at
least Android 11, 12 and 13) which incorrectly uses this
UNPREDICTABLE insn on the assumption that it does a single register
load, which is (presumably) what it happens to do on real hardware,
and is also what it does on the equivalent A32 encoding.

Revert to the pre-4b222545dbf30 behaviour of not UNDEFing
for this T32 encoding.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1799
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230927101853.39288-1-peter.maydell@linaro.org
2023-10-19 14:32:13 +01:00
..
alpha meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
arm target/arm: Permit T32 LDM with single register 2023-10-19 14:32:13 +01:00
avr meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
cris meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
hexagon target/hexagon: avoid invalid escape in Python string 2023-10-17 15:20:53 +02:00
hppa meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
i386 target/i386: check intercept for XSETBV 2023-10-17 15:20:53 +02:00
loongarch target/loongarch: Add preldx instruction 2023-10-13 09:50:16 +08:00
m68k meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
microblaze meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
mips meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
nios2 meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
openrisc meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
ppc target/ppc: Remove references to gdb_has_xml 2023-10-11 08:46:33 +01:00
riscv target/riscv: Fix vfwmaccbf16.vf 2023-10-12 12:50:13 +10:00
rx meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
s390x hw/core/cpu: Return static value with gdb_arch_name() 2023-10-11 08:46:33 +01:00
sh4 target/sh4: Disable decode_gusa when plugins enabled 2023-10-11 08:46:36 +01:00
sparc meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
tricore hw/core/cpu: Return static value with gdb_arch_name() 2023-10-11 08:46:33 +01:00
xtensa meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00