Philippe Mathieu-Daudé 3810e17173 target/riscv: Move has_work() from CPUClass to SysemuCPUOps ... Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250125170125.32855-17-philmd@linaro.org>		2025-03-09 17:00:47 +01:00
..
insn_trans	target/riscv: Add CTR sctrclr instruction.	2025-03-04 15:42:54 +10:00
kvm	accel: Rename 'hw/core/accel-cpu.h' -> 'accel/accel-cpu-target.h'	2025-03-06 15:46:17 +01:00
tcg	accel: Rename 'hw/core/accel-cpu.h' -> 'accel/accel-cpu-target.h'	2025-03-06 15:46:17 +01:00
arch_dump.c	include: Rename sysemu/ -> system/	2024-12-20 17:44:56 +01:00
bitmanip_helper.c
common-semi-target.h
cpu-param.h	target/*: Remove TARGET_LONG_BITS from cpu-param.h	2025-02-08 12:41:33 -08:00
cpu-qom.h	target/riscv: add RVA23S64 profile	2025-03-04 15:42:54 +10:00
cpu.c	target/riscv: Move has_work() from CPUClass to SysemuCPUOps	2025-03-09 17:00:47 +01:00
cpu.h	target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL	2025-03-06 15:46:18 +01:00
cpu_bits.h	target/riscv: Fix the hpmevent mask	2025-03-04 15:42:54 +10:00
cpu_cfg.h	target/riscv/cpu.c: create flag for ziccrse	2025-03-04 15:42:54 +10:00
cpu_helper.c	exec: Declare tlb_set_page() in 'exec/cputlb.h'	2025-03-08 07:56:14 -08:00
cpu_user.h	target/riscv: zicfilp lpad impl and branch tracking	2024-10-30 11:22:08 +10:00
cpu_vendorid.h
crypto_helper.c
csr.c	exec: Declare tlb_flush*() in 'exec/cputlb.h'	2025-03-08 07:56:14 -08:00
debug.c	target/riscv/debug.c: use wp size = 4 for 32-bit CPUs	2025-03-04 15:42:54 +10:00
debug.h	target/riscv: Add textra matching condition for the triggers	2024-10-02 15:11:51 +10:00
fpu_helper.c
gdbstub.c	riscv/gdbstub: add V bit to priv reg	2025-01-19 09:44:34 +10:00
helper.h	target/riscv: Add CTR sctrclr instruction.	2025-03-04 15:42:54 +10:00
insn16.decode	target/riscv: compressed encodings for sspush and sspopchk	2024-10-30 11:22:08 +10:00
insn32.decode	target/riscv: Add CTR sctrclr instruction.	2025-03-04 15:42:54 +10:00
instmap.h
internals.h	target/riscv: Move has_work() from CPUClass to SysemuCPUOps	2025-03-09 17:00:47 +01:00
Kconfig	target/riscv/cpu_helper: Fix linking problem with semihosting disabled	2024-10-02 15:11:51 +10:00
m128_helper.c
machine.c	target/riscv: machine: Add Control Transfer Record state description	2025-03-04 15:42:54 +10:00
meson.build
monitor.c	target/riscv: remove break after g_assert_not_reached()	2024-09-24 13:53:35 +02:00
op_helper.c	exec: Declare tlb_flush*() in 'exec/cputlb.h'	2025-03-08 07:56:14 -08:00
pmp.c	exec: Declare tlb_flush*() in 'exec/cputlb.h'	2025-03-08 07:56:14 -08:00
pmp.h	target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0	2025-01-19 09:44:34 +10:00
pmu.c	target/riscv: Mask out upper sscofpmf bits during validation	2025-03-04 15:42:54 +10:00
pmu.h	target/riscv: More accurately model priv mode filtering.	2024-07-18 12:08:45 +10:00
riscv-qmp-cmds.c	qapi: Move include/qapi/qmp/ to include/qobject/	2025-02-10 15:33:16 +01:00
sbi_ecall_interface.h
th_csr.c
time_helper.c	target/riscv: Stop timer with infinite timecmp	2024-10-02 15:11:51 +10:00
time_helper.h
trace-events	target/riscv: add trace in riscv_raise_exception()	2025-01-19 09:44:34 +10:00
trace.h
translate.c	target/riscv: Add support to record CTR entries.	2025-03-04 15:42:54 +10:00
vcrypto_helper.c
vector_helper.c	target/riscv: rvv: Fix unexpected behavior of vector reduction instructions when vl is 0	2025-03-04 15:42:54 +10:00
vector_internals.c
vector_internals.h	target/riscv: Include missing headers in 'vector_internals.h'	2024-12-20 11:22:47 +10:00
xthead.decode
XVentanaCondOps.decode
zce_helper.c