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qemu-cr16/target/mips/sysemu
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Yongbok Kim 59e7592756 target/mips: Migrate TLB MemoryMapID register 
Include CP0 MemoryMapID register in migration state.

Fixes: 99029be1c2 ("target/mips: Add implementation of GINVT instruction")
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
Reviewed-by: Aleksandar Rikalo <arikalo@gmail.com>
Message-ID: <AM9PR09MB4851FB6034EDB7FA191BA47E84402@AM9PR09MB4851.eurprd09.prod.outlook.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-03 05:49:12 -03:00
..
addr.c mips: Remove support for trap and emulate KVM 2023-01-13 09:32:32 +01:00
cp0.c target/mips: Move CP0 helpers to sysemu/cp0.c 2021-05-02 16:49:35 +02:00
cp0_timer.c hw/mips: Merge 'hw/mips/cpudevs.h' with 'target/mips/cpu.h' 2023-10-19 23:13:27 +02:00
machine.c target/mips: Migrate TLB MemoryMapID register 2024-11-03 05:49:12 -03:00
meson.build meson: Replace softmmu_ss -> system_ss 2023-06-20 10:01:30 +02:00
mips-qmp-cmds.c target: Use generic cpu_model_from_type() 2024-01-05 16:20:14 +01:00
physaddr.c exec/cpu: Extract page-protection definitions to page-protection.h 2024-05-06 11:17:15 +02:00