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Jamin Lin 8107448de7 hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1 
The design of INTC controllers has significantly changed in AST2700 A1.

There are a total of 480 interrupt sources in AST2700 A1. For interrupt numbers
from 0 to 127, they can route directly to PSP, SSP, and TSP. Due to the
limitation of interrupt numbers of processors, the interrupts are merged every
32 sources for interrupt numbers greater than 127.

There are two levels of interrupt controllers, INTC(CPUD Die) and INTCIO
(IO Die). The interrupt sources of INTC are the interrupt numbers from INTC_0 to
INTC_127 and interrupts from INTCIO. The interrupt sources of INTCIO are the
interrupt numbers greater than INTC_127. INTC_IO controls the interrupts
INTC_128 to INTC_319 only.

Currently, only GIC 192 to 201 are supported, and their source interrupts are
from INTCIO and connected to INTC at input pin 0 and output pins 0 to 9 for
GIC 192-201.

The design of the orgates for GICINT 196 is as follows:
It has interrupt sources ranging from 0 to 31, with its output pin connected to
INTCIO "T0 GICINT_196". The output pin is then connected to INTC "GIC_192_201"
at bit 4, and its bit 4 output should be connected to GIC 196.
The design of INTC GIC_192_201 have 10 output pins, mapped as following:
Bit 0 -> GIC 192
Bit 1 -> GIC 193
Bit 2 -> GIC 194
Bit 3 -> GIC 195
Bit 4 -> GIC 196

To support both AST2700 A1 and A0, INTC input pins 1 to 9 and output pins
10 to 18 remain to support GIC 128-136, which source interrupts from INTC.
These will be removed if we decide not to support AST2700 A0 in the future.

|-------------------------------------------------------------------------------------------------------|
|                                                   AST2700 A1 Design                                   |
|           To GICINT196                                                                                |
|                                                                                                       |
|   ETH1    |-----------|                    |--------------------------|        |--------------|       |
|  -------->|0          |                    |         INTCIO           |        |  orgates[0]  |       |
|   ETH2    |          4|   orgates[0]------>|inpin[0]-------->outpin[0]|------->| 0            |       |
|  -------->|1         5|   orgates[1]------>|inpin[1]-------->outpin[1]|------->| 1            |       |
|   ETH3    |          6|   orgates[2]------>|inpin[2]-------->outpin[2]|------->| 2            |       |
|  -------->|2        19|   orgates[3]------>|inpin[3]-------->outpin[3]|------->| 3  OR[0:9]   |-----| |
|   UART0   |         20|-->orgates[4]------>|inpin[4]-------->outpin[4]|------->| 4            |     | |
|  -------->|7        21|   orgates[5]------>|inpin[5]-------->outpin[5]|------->| 5            |     | |
|   UART1   |         22|   orgates[6]------>|inpin[6]-------->outpin[6]|------->| 6            |     | |
|  -------->|8        23|   orgates[7]------>|inpin[7]-------->outpin[7]|------->| 7            |     | |
|   UART2   |         24|   orgates[8]------>|inpin[8]-------->outpin[8]|------->| 8            |     | |
|  -------->|9        25|   orgates[9]------>|inpin[9]-------->outpin[9]|------->| 9            |     | |
|   UART3   |         26|                    |--------------------------|        |--------------|     | |
|  ---------|10       27|                                                                             | |
|   UART5   |         28|                                                                             | |
|  -------->|11       29|                                                                             | |
|   UART6   |           |                                                                             | |
|  -------->|12       30|     |-----------------------------------------------------------------------| |
|   UART7   |         31|     |                                                                         |
|  -------->|13         |     |                                                                         |
|   UART8   |  OR[0:31] |     |                |------------------------------|           |----------|  |
|  -------->|14         |     |                |            INTC              |           |     GIC  |  |
|   UART9   |           |     |                |inpin[0:0]--------->outpin[0] |---------->|192       |  |
|  -------->|15         |     |                |inpin[0:1]--------->outpin[1] |---------->|193       |  |
|   UART10  |           |     |                |inpin[0:2]--------->outpin[2] |---------->|194       |  |
|  -------->|16         |     |                |inpin[0:3]--------->outpin[3] |---------->|195       |  |
|   UART11  |           |     |--------------> |inpin[0:4]--------->outpin[4] |---------->|196       |  |
|  -------->|17         |                      |inpin[0:5]--------->outpin[5] |---------->|197       |  |
|   UART12  |           |                      |inpin[0:6]--------->outpin[6] |---------->|198       |  |
|  -------->|18         |                      |inpin[0:7]--------->outpin[7] |---------->|199       |  |
|           |-----------|                      |inpin[0:8]--------->outpin[8] |---------->|200       |  |
|                                              |inpin[0:9]--------->outpin[9] |---------->|201       |  |
|-------------------------------------------------------------------------------------------------------|
|-------------------------------------------------------------------------------------------------------|
|  ETH1    |-----------|     orgates[1]------->|inpin[1]----------->outpin[10]|---------->|128       |  |
| -------->|0          |     orgates[2]------->|inpin[2]----------->outpin[11]|---------->|129       |  |
|  ETH2    |          4|     orgates[3]------->|inpin[3]----------->outpin[12]|---------->|130       |  |
| -------->|1         5|     orgates[4]------->|inpin[4]----------->outpin[13]|---------->|131       |  |
|  ETH3    |          6|---->orgates[5]------->|inpin[5]----------->outpin[14]|---------->|132       |  |
| -------->|2        19|     orgates[6]------->|inpin[6]----------->outpin[15]|---------->|133       |  |
|  UART0   |         20|     orgates[7]------->|inpin[7]----------->outpin[16]|---------->|134       |  |
| -------->|7        21|     orgates[8]------->|inpin[8]----------->outpin[17]|---------->|135       |  |
|  UART1   |         22|     orgates[9]------->|inpin[9]----------->outpin[18]|---------->|136       |  |
| -------->|8        23|                       |------------------------------|           |----------|  |
|  UART2   |         24|                                                                                |
| -------->|9        25|                       AST2700 A0 Design                                        |
|  UART3   |         26|                                                                                |
| -------->|10       27|                                                                                |
|  UART5   |         28|                                                                                |
| -------->|11       29| GICINT132                                                                      |
|  UART6   |           |                                                                                |
| -------->|12       30|                                                                                |
|  UART7   |         31|                                                                                |
| -------->|13         |                                                                                |
|  UART8   |  OR[0:31] |                                                                                |
| -------->|14         |                                                                                |
|  UART9   |           |                                                                                |
| -------->|15         |                                                                                |
|  UART10  |           |                                                                                |
| -------->|16         |                                                                                |
|  UART11  |           |                                                                                |
| -------->|17         |                                                                                |
|  UART12  |           |                                                                                |
| -------->|18         |                                                                                |
|          |-----------|                                                                                |
|                                                                                                       |
|-------------------------------------------------------------------------------------------------------|

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-22-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-03-09 14:36:53 +01:00
..
acpi hw/acpi/ghes: Make ghes_record_cper_errors() static 2025-03-04 14:45:34 +01:00
adc hw/adc: Remove MAX111X device 2024-10-15 15:16:17 +01:00
arm hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1 2025-03-09 14:36:53 +01:00
audio
block hw/block: Remove ecc 2024-10-15 15:16:17 +01:00
char hw/char/imx_serial: Fix reset value of UFCR register 2025-01-27 13:50:14 +00:00
core cpus: Restrict cpu_get_memory_mapping() to system emulation 2025-03-06 15:46:18 +01:00
cpu
cxl hw/cxl: Introduce CXL_T3_MSIX_VECTOR enumeration 2025-02-21 07:18:42 -05:00
display
dma include: Rename sysemu/ -> system/ 2024-12-20 17:44:56 +01:00
firmware
fsi
gpio hw/gpio/aspeed: Support different memory region ops 2024-10-24 07:57:47 +02:00
hyperv include: Rename sysemu/ -> system/ 2024-12-20 17:44:56 +01:00
i2c
i386 hw/i386/pc: Remove unused pc_compat_2_3 declarations 2025-01-30 13:01:22 +03:00
ide include: Rename sysemu/ -> system/ 2024-12-20 17:44:56 +01:00
input
intc hw/intc/aspeed: Add Support for AST2700 INTCIO Controller 2025-03-09 14:36:53 +01:00
ipack hw/ipack: Remove legacy qemu_allocate_irqs() use 2025-01-31 19:36:44 +01:00
ipmi
isa include: Rename sysemu/ -> system/ 2024-12-20 17:44:56 +01:00
loongarch hw/loongarch/virt: Update the ACPI table for hotplug cpu 2025-03-05 09:39:18 +08:00
m68k
mem
mips hw/mips/cps: Set the vCPU 'cpu-big-endian' property 2024-10-15 12:21:06 -03:00
misc hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions 2025-03-09 14:36:53 +01:00
net hw/net: Add NPCM8XX PCS Module 2025-02-20 15:22:22 +00:00
nubus
nvram include: Rename sysemu/ -> system/ 2024-12-20 17:44:56 +01:00
openrisc hw/openrisc: Support monitor dumpdtb command 2025-02-24 15:03:42 +00:00
pci pcie, virtio: Remove redundant pm_cap 2025-03-06 06:47:33 +01:00
pci-bridge hw/pci-bridge/cxl-upstream: Add properties to control link speed and width 2024-11-04 16:03:24 -05:00
pci-host hw/arm/fsl-imx8mp: Add PCIe support 2025-02-25 17:02:34 +00:00
ppc include: Rename sysemu/ -> system/ 2024-12-20 17:44:56 +01:00
remote
riscv target/riscv: Handle Smrnmi interrupt and exception 2025-01-19 09:44:34 +10:00
rtc
rx
s390x s390x/pci: indicate QEMU supports relaxed translation for passthrough 2025-03-07 09:24:00 +01:00
scsi
sd hw/sd: Remove unused legacy functions, stop killing mammoths 2025-01-31 19:36:44 +01:00
sensor
sh4
southbridge
sparc
ssi hw/ssi: Make flash size a property in NPCM7XX FIU 2025-02-20 14:20:29 +00:00
timer hw/arm/fsl-imx8mp: Implement general purpose timers 2025-02-25 17:03:46 +00:00
tricore include: Rename sysemu/ -> system/ 2024-12-20 17:44:56 +01:00
uefi hw/uefi: add include/hw/uefi/var-service.h 2025-03-04 12:01:42 +01:00
usb hw/usb/hcd-dwc3: Align global registers size with Linux 2025-02-25 15:32:58 +00:00
vfio vfio/migration: Add x-migration-multifd-transfer VFIO property 2025-03-06 06:47:34 +01:00
virtio hw/vmapple/virtio-blk: Add support for apple virtio-blk 2025-03-04 14:45:34 +01:00
vmapple hw/vmapple/virtio-blk: Add support for apple virtio-blk 2025-03-04 14:45:34 +01:00
watchdog
xen hw/xen/xen-legacy-backend: Remove unused 'net/net.h' header 2025-03-04 14:45:34 +01:00
xtensa
boards.h i386/cpu: add has_caches flag to check smp_cache configuration 2025-02-25 16:18:12 +01:00
clock.h clock: clear callback on unparent 2024-12-10 18:49:24 +01:00
elf_ops.h.inc
fw-path-provider.h
hotplug.h
hw.h
irq.h hw/irq: Introduce qemu_init_irqs() helper 2025-01-31 19:36:44 +01:00
loader-fit.h hw/mips/boston: Support dumpdtb monitor commands 2025-02-24 15:03:42 +00:00
loader.h hw/loader: Pass ELFDATA endian order argument to load_elf() 2025-01-31 19:36:44 +01:00
nmi.h
or-irq.h
platform-bus.h
ptimer.h
qdev-clock.h
qdev-core.h hw/qdev: Factor qdev_hotunplug_allowed() out 2025-01-13 17:16:03 +01:00
qdev-dma.h
qdev-properties-system.h hw/vmapple/virtio-blk: Add support for apple virtio-blk 2025-03-04 14:45:34 +01:00
qdev-properties.h qdev: Rename PropertyInfo member @name to @type 2025-03-06 10:30:58 +01:00
register.h
registerfields.h
resettable.h
stream.h
sysbus.h hw/sysbus: Introduce TYPE_DYNAMIC_SYS_BUS_DEVICE 2025-02-16 14:25:07 +01:00
usb.h hw/usb: Inline usb_new() 2025-01-13 17:07:00 +01:00
vmstate-if.h