dfff1000fe
Implement a model of the Neoverse N2 CPU. This is an Armv9.0-A processor very similar to the Cortex-A710. The differences are: * no FEAT_EVT * FEAT_DGH (data gathering hint) * FEAT_NV (not yet implemented in QEMU) * Statistical Profiling Extension (not implemented in QEMU) * 48 bit physical address range, not 40 * CTR_EL0.DIC = 1 (no explicit icache cleaning needed) * PMCR_EL0.N = 6 (always 6 PMU counters, not 20) Because it has 48-bit physical address support, we can use this CPU in the sbsa-ref board as well as the virt board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20230915185453.1871167-3-peter.maydell@linaro.org |
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| .. | ||
| _templates | ||
| about | ||
| config | ||
| devel | ||
| interop | ||
| specs | ||
| sphinx | ||
| sphinx-static | ||
| spin | ||
| system | ||
| tools | ||
| user | ||
| block-replication.txt | ||
| bypass-iommu.txt | ||
| COLO-FT.txt | ||
| colo-proxy.txt | ||
| conf.py | ||
| defs.rst.inc | ||
| igd-assign.txt | ||
| image-fuzzer.txt | ||
| index.rst | ||
| memory-hotplug.txt | ||
| meson.build | ||
| multi-thread-compression.txt | ||
| multiseat.txt | ||
| nvdimm.txt | ||
| pci_expander_bridge.txt | ||
| pcie.txt | ||
| pcie_pci_bridge.txt | ||
| pcie_sriov.txt | ||
| pvrdma.txt | ||
| qcow2-cache.txt | ||
| qdev-device-use.txt | ||
| qemu-option-trace.rst.inc | ||
| qemupciserial.inf | ||
| rdma.txt | ||
| spice-port-fqdn.txt | ||
| throttle.txt | ||
| xbzrle.txt | ||
| xen-save-devices-state.txt | ||