qemu-cr16/target
Vacha Bhavsar 030f0ba117 target/arm: Added support for SME register exposure to GDB
The QEMU GDB stub does not expose the ZA storage SME register to GDB
via the remote serial protocol, which can be a useful functionality
to debug SME code.  To provide this functionality for AArch64
targets, this patch registers the SME register set with the GDB stub.
To do so, this patch implements the aarch64_gdb_get_sme_reg() and
aarch64_gdb_set_sme_reg() functions to specify how to get and set the
SME registers, and the arm_gen_dynamic_smereg_feature() function to
generate the target description in XML format to indicate the target
architecture supports SME.  Finally, this patch includes a
dyn_smereg_feature structure to hold this GDB XML description of the
SME registers for each CPU.

Note that according to the GDB documentation the ZA register is
defined as a vector of bytes; however the target description xml
retrieved when using gdb natively on a host with SME capabilities
represents the ZA register as a vector of vectors of bytes, so this
is a GDB documentation error.  We follow GDB's own gdbstub
implementation and represent the ZA register as a vector of vectors
of bytes as is done by GDB here:

5cce2b7006/gdb/features/aarch64-sme.c (L50)

Signed-off-by: Vacha Bhavsar <vacha.bhavsar@oss.qualcomm.com>
Message-id: 20250909161012.2561593-3-vacha.bhavsar@oss.qualcomm.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: fixed minor checkpatch nits]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-09-16 17:31:54 +01:00
..
alpha add cpu_test_interrupt()/cpu_set_interrupt() helpers and use them tree wide 2025-08-29 12:48:14 +02:00
arm target/arm: Added support for SME register exposure to GDB 2025-09-16 17:31:54 +01:00
avr add cpu_test_interrupt()/cpu_set_interrupt() helpers and use them tree wide 2025-08-29 12:48:14 +02:00
hexagon accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
hppa add cpu_test_interrupt()/cpu_set_interrupt() helpers and use them tree wide 2025-08-29 12:48:14 +02:00
i386 i386/kvm/vmsr_energy: Plug memory leak on failure to connect socket 2025-09-01 13:10:55 +02:00
loongarch loongarch queue 2025-09-01 11:15:06 +10:00
m68k add cpu_test_interrupt()/cpu_set_interrupt() helpers and use them tree wide 2025-08-29 12:48:14 +02:00
microblaze add cpu_test_interrupt()/cpu_set_interrupt() helpers and use them tree wide 2025-08-29 12:48:14 +02:00
mips target/mips: fix TLB huge page check to use 64-bit shift 2025-09-02 17:57:05 +02:00
openrisc add cpu_test_interrupt()/cpu_set_interrupt() helpers and use them tree wide 2025-08-29 12:48:14 +02:00
ppc hw/ppc: Fix build error with CONFIG_POWERNV disabled 2025-09-02 17:57:05 +02:00
riscv target/riscv: Restrict midelegh access to S-mode harts 2025-07-30 10:59:26 +10:00
rx add cpu_test_interrupt()/cpu_set_interrupt() helpers and use them tree wide 2025-08-29 12:48:14 +02:00
s390x add cpu_test_interrupt()/cpu_set_interrupt() helpers and use them tree wide 2025-08-29 12:48:14 +02:00
sh4 add cpu_test_interrupt()/cpu_set_interrupt() helpers and use them tree wide 2025-08-29 12:48:14 +02:00
sparc add cpu_test_interrupt()/cpu_set_interrupt() helpers and use them tree wide 2025-08-29 12:48:14 +02:00
tricore target: Use cpu_pointer_wrap_uint32 for 32-bit targets 2025-05-28 08:08:48 +01:00
xtensa target/xtensa: replace FSF postal address with licenses URL 2025-06-26 00:42:37 +02:00
Kconfig target/cris: Remove the deprecated CRIS target 2024-09-13 20:11:13 +02:00
meson.build target/cris: Remove the deprecated CRIS target 2024-09-13 20:11:13 +02:00