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Peter Maydell a146c6f88c target-arm queue: 
* Implement FEAT_ECV
  * STM32L4x5: Implement GPIO device
  * Fix 32-bit SMOPA
  * Refactor v7m related code from cpu32.c into its own file
  * hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later
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Merge tag 'pull-target-arm-20240308' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * Implement FEAT_ECV
 * STM32L4x5: Implement GPIO device
 * Fix 32-bit SMOPA
 * Refactor v7m related code from cpu32.c into its own file
 * hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later

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# gpg: Signature made Fri 08 Mar 2024 15:49:49 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20240308' of https://git.linaro.org/people/pmaydell/qemu-arm:
  target/arm: Move v7m-related code from cpu32.c into a separate file
  hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later
  target/arm: Fix 32-bit SMOPA
  tests/qtest: Add STM32L4x5 GPIO QTest testcase
  hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC
  hw/gpio: Implement STM32L4x5 GPIO
  target/arm: Enable FEAT_ECV for 'max' CPU
  target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling
  target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0
  target/arm: Implement new FEAT_ECV trap bits
  target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written
  target/arm: use FIELD macro for CNTHCTL bit definitions
  target/arm: Timer _EL02 registers UNDEF for E2H == 0
  target/arm: Move some register related defines to internals.h

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-08 18:19:09 +00:00
..
alpha target/alpha: Enable TARGET_PAGE_BITS_VARY for user-only 2024-02-29 11:35:37 -10:00
arm target/arm: Move v7m-related code from cpu32.c into a separate file 2024-03-08 14:45:03 +00:00
avr gdbstub: Infer number of core registers from XML 2024-02-28 09:09:58 +00:00
cris include/exec: Change cpu_mmu_index argument to CPUState 2024-02-03 16:46:10 +10:00
hexagon gdbstub: Infer number of core registers from XML 2024-02-28 09:09:58 +00:00
hppa target/hppa: Restore unwind_breg before calculating ior 2024-03-03 06:41:19 +01:00
i386 * target/i386: Fix physical address truncation on 32-bit PAE 2024-02-28 14:23:21 +00:00
loongarch target/loongarch: honour show_opcodes when disassembling 2024-03-06 12:35:51 +00:00
m68k gdbstub: Infer number of core registers from XML 2024-02-28 09:09:58 +00:00
microblaze gdbstub: Infer number of core registers from XML 2024-02-28 09:09:58 +00:00
mips target/mips: Remove the unused DisasContext::saar field 2024-02-15 15:53:12 +01:00
nios2 kconfig: use "select" to enable semihosting 2024-02-09 17:52:30 +00:00
openrisc include/exec: Change cpu_mmu_index argument to CPUState 2024-02-03 16:46:10 +10:00
ppc target/ppc: Enable TARGET_PAGE_BITS_VARY for user-only 2024-02-29 11:35:37 -10:00
riscv target/riscv: Fix privilege mode of G-stage translation for debugging 2024-03-08 20:48:03 +10:00
rx gdbstub: Infer number of core registers from XML 2024-02-28 09:09:58 +00:00
s390x gdbstub: Infer number of core registers from XML 2024-02-28 09:09:58 +00:00
sh4 include/exec: Implement cpu_mmu_index generically 2024-02-03 16:46:10 +10:00
sparc accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull 2024-03-05 13:22:56 +00:00
tricore include/exec: Change cpu_mmu_index argument to CPUState 2024-02-03 16:46:10 +10:00
xtensa kconfig: use "select" to enable semihosting 2024-02-09 17:52:30 +00:00
Kconfig
meson.build target: Make qemu_target_page_mask() available for *-user 2024-01-29 21:04:10 +10:00
target-common.c target: Make qemu_target_page_mask() available for *-user 2024-01-29 21:04:10 +10:00