qemu-cr16/target/riscv/meson.build
Pierrick Bouvier 9e65902904 include/semihosting/common-semi: extract common_semi API
We transform target/{arm,riscv}/common-semi-target.h headers to proper
compilation units, and use them in arm-compat-semi.c.

This way, we can include only the declaration header (which is target
agnostic), and selectively link the appropriate implementation based on
current target.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20250822150058.18692-8-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-ID: <20250922093711.2768983-11-alex.bennee@linaro.org>
2025-09-26 09:55:19 +01:00

49 lines
1.1 KiB
Meson

# FIXME extra_args should accept files()
gen = [
decodetree.process('insn16.decode', extra_args: ['--static-decode=decode_insn16', '--insnwidth=16']),
decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
decodetree.process('xthead.decode', extra_args: '--static-decode=decode_xthead'),
decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decode=decode_XVentanaCodeOps'),
]
riscv_ss = ss.source_set()
riscv_ss.add(gen)
riscv_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING',
if_true: files('common-semi-target.c'))
riscv_ss.add(files(
'cpu.c',
'cpu_helper.c',
'csr.c',
'fpu_helper.c',
'gdbstub.c',
'op_helper.c',
'vector_helper.c',
'vector_internals.c',
'bitmanip_helper.c',
'translate.c',
'm128_helper.c',
'crypto_helper.c',
'zce_helper.c',
'vcrypto_helper.c'
))
riscv_system_ss = ss.source_set()
riscv_system_ss.add(files(
'arch_dump.c',
'pmp.c',
'debug.c',
'monitor.c',
'machine.c',
'pmu.c',
'th_csr.c',
'time_helper.c',
'riscv-qmp-cmds.c',
))
subdir('tcg')
subdir('kvm')
target_arch += {'riscv': riscv_ss}
target_system_arch += {'riscv': riscv_system_ss}