Paolo Bonzini bf13bfab08 i386: implement IGNNE ... Change the handling of port F0h writes and FPU exceptions to implement IGNNE. The implementation mixes a bit what the chipset and processor do in real hardware, but the effect is the same as what happens with actual FERR# and IGNNE# pins: writing to port F0h asserts IGNNE# in addition to lowering FP_IRQ; while clearing the SE bit in the FPU status word deasserts IGNNE#. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>		2019-10-26 15:38:07 +02:00
..
alpha	target/alpha: Tidy helper_fp_exc_raise_s	2019-09-26 19:00:53 +01:00
arm	target/arm: Rely on hflags correct in cpu_get_tb_cpu_state	2019-10-24 17:16:28 +01:00
cris
hppa	target/hppa: prevent trashing of temporary in do_depw_sar()	2019-09-14 15:39:24 -04:00
i386	i386: implement IGNNE	2019-10-26 15:38:07 +02:00
lm32
m68k	target/m68k/fpu_helper.c: rename the access arguments	2019-09-19 12:12:19 +02:00
microblaze	tcg: TCGMemOp is now accelerator independent MemOp	2019-09-03 08:30:38 -07:00
mips	target/mips: Refactor handling of vector compare 'less than' (signed) instructions	2019-10-25 18:37:01 +02:00
moxie
nios2
openrisc	target/openrisc: Update cpu "any" to v1.3	2019-09-04 13:01:56 -07:00
ppc	core: replace getpagesize() with qemu_real_host_page_size	2019-10-26 15:38:06 +02:00
riscv	gdbstub: riscv: fix the fflags registers	2019-09-17 08:42:50 -07:00
s390x	s390x/kvm: Set default cpu model for all machine classes	2019-10-21 18:03:08 +02:00
sh4
sparc	target/sparc: Switch to do_transaction_failed() hook	2019-09-17 12:01:00 +01:00
tilegx	tcg: TCGMemOp is now accelerator independent MemOp	2019-09-03 08:30:38 -07:00
tricore	tcg: TCGMemOp is now accelerator independent MemOp	2019-09-03 08:30:38 -07:00
unicore32
xtensa	target/xtensa: regenerate and re-import test_mmuhifi_c3 core	2019-10-18 19:54:27 -07:00