qemu-cr16/target/openrisc
Philippe Mathieu-Daudé 46a2cfc448 gdbstub: Clarify no more than @gdb_num_core_regs can be accessed
Both CPUClass::gdb_read_register() and CPUClass::gdb_write_register()
handlers are called from common gdbstub code, and won't be called with
register index over CPUClass::gdb_num_core_regs:

  int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
  {
      CPUClass *cc = CPU_GET_CLASS(cpu);

      if (reg < cc->gdb_num_core_regs) {
          return cc->gdb_read_register(cpu, buf, reg);
      }
      ...
  }

  static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg)
  {
      CPUClass *cc = CPU_GET_CLASS(cpu);

      if (reg < cc->gdb_num_core_regs) {
          return cc->gdb_write_register(cpu, mem_buf, reg);
      }
      ...
  }

Clarify that in CPUClass docstring, and remove unreachable code on
the microblaze and openrisc implementations.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250122093028.52416-3-philmd@linaro.org>
2025-03-06 15:46:17 +01:00
..
cpu-param.h target/*: Remove TARGET_LONG_BITS from cpu-param.h 2025-02-08 12:41:33 -08:00
cpu-qom.h target: Move ArchCPUClass definition to 'cpu.h' 2023-11-07 13:08:48 +01:00
cpu.c accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
cpu.h accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
disas.c meson: target 2020-08-21 06:30:35 -04:00
exception.c compiler.h: replace QEMU_NORETURN with G_NORETURN 2022-04-21 17:03:51 +04:00
exception.h compiler.h: replace QEMU_NORETURN with G_NORETURN 2022-04-21 17:03:51 +04:00
exception_helper.c compiler.h: replace QEMU_NORETURN with G_NORETURN 2022-04-21 17:03:51 +04:00
fpu_helper.c target/openrisc: Set PC to cpu state on FPU exception 2023-05-11 15:40:03 +01:00
gdbstub.c gdbstub: Clarify no more than @gdb_num_core_regs can be accessed 2025-03-06 15:46:17 +01:00
helper.h target/openrisc: Implement unordered fp comparisons 2019-09-04 12:57:59 -07:00
insns.decode target/openrisc: Implement l.adrp 2019-09-04 12:59:00 -07:00
interrupt.c target/openrisc: Prefer fast cpu_env() over slower CPU QOM cast macro 2024-03-12 12:04:24 +01:00
interrupt_helper.c target/openrisc: Fix LGPL version number 2019-01-30 11:01:36 +01:00
Kconfig kconfig: express dependency of individual boards on libfdt 2024-05-10 15:45:15 +02:00
machine.c target/openrisc: Constify VMState in machine.c 2023-12-29 11:17:30 +11:00
meson.build meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
mmu.c exec/cpu: Extract page-protection definitions to page-protection.h 2024-05-06 11:17:15 +02:00
sys_helper.c system/cpus: rename qemu_mutex_lock_iothread() to bql_lock() 2024-01-08 10:45:43 -05:00
translate.c accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00