6ba430b58a
The RAS feature has a block of memory-mapped registers at offset 0x5000 within the PPB. For a "minimal RAS" implementation we provide no error records and so the only registers that exist in the block are ERRIIDR and ERRDEVID. The "RAZ/WI for privileged, BusFault for nonprivileged" behaviour of the "nvic-default" region is actually valid for minimal-RAS, so the main benefit of providing an explicit implementation of the register block is more accurate LOG_UNIMP messages, and a framework for where we could add a real RAS implementation later if necessary. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201119215617.29887-27-peter.maydell@linaro.org |
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| .. | ||
| allwinner-a10-pic.h | ||
| arm_gic.h | ||
| arm_gic_common.h | ||
| arm_gicv3.h | ||
| arm_gicv3_common.h | ||
| arm_gicv3_its_common.h | ||
| armv7m_nvic.h | ||
| aspeed_vic.h | ||
| bcm2835_ic.h | ||
| bcm2836_control.h | ||
| heathrow_pic.h | ||
| i8259.h | ||
| ibex_plic.h | ||
| imx_avic.h | ||
| imx_gpcv2.h | ||
| intc.h | ||
| mips_gic.h | ||
| realview_gic.h | ||
| rx_icu.h | ||
| sifive_clint.h | ||
| sifive_plic.h | ||
| xlnx-pmu-iomod-intc.h | ||
| xlnx-zynqmp-ipi.h | ||