qemu-cr16/target
Daniel Henrique Barboza bf031e257d target/riscv/csr.c: fix deadcode in rmw_xireg()
Coverity found a DEADCODE issue in rmw_xireg() claiming that we can't
reach 'RISCV_EXCP_VIRT_INSTRUCTION_FAULT' at the 'done' label:

done:
    if (ret) {
        return (env->virt_enabled && virt) ?
               RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
    }
    return RISCV_EXCP_NONE;

This happens because the 'virt' flag, which is only used by 'done', is
set to 'false' and it will always remain 'false' in any condition where
we'll jump to 'done':

    switch (csrno) {
    (...)
    case CSR_VSIREG:
        isel = env->vsiselect;
        virt = true;
        break;
    default:
        goto done;
    };

'virt = true' will never reach 'done' because we have a if/else-if/else
block right before the label that will always return:

    if (xiselect_aia_range(isel)) {
        return ...
    } else if (...) {
        return ...
    } else {
        return RISCV_EXCP_ILLEGAL_INST;
    }

All this means that we can preserve the current logic by reducing the
'done' label to:

done:
    if (ret) {
        return RISCV_EXCP_ILLEGAL_INST;
    }
    return RISCV_EXCP_NONE;

The flag 'virt' is now unused. Remove it.

Fix the 'goto done' identation while we're at it.

Resolves: Coverity CID 1590359
Fixes: dc0280723d ("target/riscv: Decouple AIA processing from xiselect and xireg")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250121184847.2109128-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-03-04 15:42:53 +10:00
..
alpha fpu: allow flushing of output denormals to be after rounding 2025-02-11 16:22:07 +00:00
arm target/arm/hvf: sign extend the data for a load operation when SSE=1 2025-02-25 15:32:58 +00:00
avr target/*: Remove TARGET_LONG_BITS from cpu-param.h 2025-02-08 12:41:33 -08:00
hexagon target/*: Remove TARGET_LONG_BITS from cpu-param.h 2025-02-08 12:41:33 -08:00
hppa fpu: Always decide snan_bit_is_one() at runtime 2025-02-25 15:32:57 +00:00
i386 * qom: Use command line syntax for default values in help 2025-03-03 10:20:59 +08:00
loongarch target/loongarch: Enable virtual extioi feature 2025-02-25 16:05:31 +08:00
m68k fpu: Move m68k_denormal fmt flag into floatx80_behaviour 2025-02-25 15:32:57 +00:00
microblaze target/*: Remove TARGET_LONG_BITS from cpu-param.h 2025-02-08 12:41:33 -08:00
mips target/mips: Use VADDR_PRIx for logging pc_next 2025-02-18 08:29:02 -08:00
openrisc target/*: Remove TARGET_LONG_BITS from cpu-param.h 2025-02-08 12:41:33 -08:00
ppc fpu: allow flushing of output denormals to be after rounding 2025-02-11 16:22:07 +00:00
riscv target/riscv/csr.c: fix deadcode in rmw_xireg() 2025-03-04 15:42:53 +10:00
rx fpu: allow flushing of output denormals to be after rounding 2025-02-11 16:22:07 +00:00
s390x QAPI patches patches for 2025-02-10 2025-02-10 10:47:31 -05:00
sh4 fpu: Always decide snan_bit_is_one() at runtime 2025-02-25 15:32:57 +00:00
sparc target/sparc: fake UltraSPARC T1 PCR and PIC registers 2025-02-18 08:29:03 -08:00
tricore fpu: allow flushing of output denormals to be after rounding 2025-02-11 16:22:07 +00:00
xtensa target/*: Remove TARGET_LONG_BITS from cpu-param.h 2025-02-08 12:41:33 -08:00
Kconfig target/cris: Remove the deprecated CRIS target 2024-09-13 20:11:13 +02:00
meson.build target/cris: Remove the deprecated CRIS target 2024-09-13 20:11:13 +02:00