7197f6f7ba
The IBM PPE42 processors support a 32-bit decrementer that can raise an external interrupt when DEC[0] transitions from a 0 to a -1 (a non-negative value to a negative value). It also continues decrementing even after this condition is met. The BookE timer is slightly different in that it raises an interrupt when the DEC value reaches 0 and stops decrementing at that point. Support a PPE42 version of the BookE timer by adding a new PPC_TIMER_PPE flag that has the timer code look for the transition from a non-negative value to a negative value and allows the value to continue decrementing. Signed-off-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250925201758.652077-8-milesg@linux.ibm.com Message-ID: <20250925201758.652077-8-milesg@linux.ibm.com> |
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| .. | ||
| fdt.h | ||
| mac_dbdma.h | ||
| openpic.h | ||
| openpic_kvm.h | ||
| pnv.h | ||
| pnv_adu.h | ||
| pnv_chip.h | ||
| pnv_chiptod.h | ||
| pnv_core.h | ||
| pnv_homer.h | ||
| pnv_i2c.h | ||
| pnv_lpc.h | ||
| pnv_n1_chiplet.h | ||
| pnv_nest_pervasive.h | ||
| pnv_occ.h | ||
| pnv_pnor.h | ||
| pnv_psi.h | ||
| pnv_sbe.h | ||
| pnv_xive.h | ||
| pnv_xscom.h | ||
| ppc.h | ||
| ppc4xx.h | ||
| ppc_e500.h | ||
| spapr.h | ||
| spapr_cpu_core.h | ||
| spapr_drc.h | ||
| spapr_irq.h | ||
| spapr_nested.h | ||
| spapr_numa.h | ||
| spapr_nvdimm.h | ||
| spapr_ovec.h | ||
| spapr_tpm_proxy.h | ||
| spapr_vio.h | ||
| spapr_xive.h | ||
| vof.h | ||
| xics.h | ||
| xics_spapr.h | ||
| xive.h | ||
| xive2.h | ||
| xive2_regs.h | ||
| xive_regs.h | ||