Palmer Dabbelt fd990e86a7 RISC-V: Add a missing "," in riscv_excp_names ... This would almost certainly cause the exception names to be reported incorrectly. Coverity found the issue (CID 1420223). As per Peter's suggestion, I've also added a comma at the end of the list to avoid the issue reappearing in the future. Fixes: ab67a1d07a ("target/riscv: Add support for the new execption numbers") Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2020-03-05 12:01:43 -08:00
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alpha
arm	target/arm: Clean address for DC ZVA	2020-03-05 16:09:21 +00:00
cris
hppa	target/hppa: Allow, but diagnose, LDCW aligned only mod 4	2020-01-27 10:49:51 -08:00
i386	Merge branch 'exec_rw_const_v4' of https://github.com/philmd/qemu into HEAD	2020-02-25 13:41:48 +01:00
lm32
m68k
microblaze	qdev: set properties with device_class_set_props()	2020-01-24 20:59:15 +01:00
mips	target/mips: Separate FPU-related helpers into their own file	2020-02-04 08:53:54 +01:00
moxie
nios2	qdev: set properties with device_class_set_props()	2020-01-24 20:59:15 +01:00
openrisc
ppc	target/ppc/cpu.h: Clean up comments in the struct CPUPPCState definition	2020-02-21 09:15:04 +11:00
riscv	RISC-V: Add a missing "," in riscv_excp_names	2020-03-05 12:01:43 -08:00
s390x	s390x: Rename and use constants for short PSW address and mask	2020-02-27 11:10:29 +01:00
sh4
sparc	qdev: set properties with device_class_set_props()	2020-01-24 20:59:15 +01:00
tilegx
tricore
unicore32
xtensa