This removes the TARGET_* conditions from all the CPU commands that are conceptually target independent. Top level stubs are provided to cope with targets which do not currently implement all of the commands. Adjust the doc comments accordingly. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20250522190542.588267-10-pierrick.bouvier@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com>
230 lines
6.2 KiB
C
230 lines
6.2 KiB
C
/*
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* QEMU PPC (monitor definitions)
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "monitor/monitor.h"
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#include "qemu/ctype.h"
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#include "monitor/hmp-target.h"
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#include "monitor/hmp.h"
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#include "qapi/error.h"
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#include "qapi/qapi-commands-machine.h"
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#include "cpu-models.h"
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#include "cpu-qom.h"
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static target_long monitor_get_ccr(Monitor *mon, const struct MonitorDef *md,
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int val)
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{
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CPUArchState *env = mon_get_cpu_env(mon);
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unsigned int u;
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u = ppc_get_cr(env);
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return u;
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}
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static target_long monitor_get_xer(Monitor *mon, const struct MonitorDef *md,
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int val)
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{
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CPUArchState *env = mon_get_cpu_env(mon);
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return cpu_read_xer(env);
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}
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static target_long monitor_get_decr(Monitor *mon, const struct MonitorDef *md,
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int val)
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{
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CPUArchState *env = mon_get_cpu_env(mon);
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if (!env->tb_env) {
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return 0;
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}
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return cpu_ppc_load_decr(env);
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}
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static target_long monitor_get_tbu(Monitor *mon, const struct MonitorDef *md,
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int val)
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{
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CPUArchState *env = mon_get_cpu_env(mon);
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if (!env->tb_env) {
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return 0;
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}
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return cpu_ppc_load_tbu(env);
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}
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static target_long monitor_get_tbl(Monitor *mon, const struct MonitorDef *md,
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int val)
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{
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CPUArchState *env = mon_get_cpu_env(mon);
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if (!env->tb_env) {
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return 0;
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}
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return cpu_ppc_load_tbl(env);
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}
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void hmp_info_tlb(Monitor *mon, const QDict *qdict)
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{
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CPUArchState *env1 = mon_get_cpu_env(mon);
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if (!env1) {
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monitor_printf(mon, "No CPU available\n");
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return;
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}
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dump_mmu(env1);
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}
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const MonitorDef monitor_defs[] = {
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{ "fpscr", offsetof(CPUPPCState, fpscr) },
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/* Next instruction pointer */
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{ "nip|pc", offsetof(CPUPPCState, nip) },
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{ "lr", offsetof(CPUPPCState, lr) },
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{ "ctr", offsetof(CPUPPCState, ctr) },
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{ "decr", 0, &monitor_get_decr, },
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{ "ccr|cr", 0, &monitor_get_ccr, },
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/* Machine state register */
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{ "xer", 0, &monitor_get_xer },
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{ "msr", offsetof(CPUPPCState, msr) },
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{ "tbu", 0, &monitor_get_tbu, },
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#if defined(TARGET_PPC64)
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{ "tb", 0, &monitor_get_tbl, },
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#else
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{ "tbl", 0, &monitor_get_tbl, },
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#endif
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{ NULL },
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};
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const MonitorDef *target_monitor_defs(void)
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{
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return monitor_defs;
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}
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static int ppc_cpu_get_reg_num(const char *numstr, int maxnum, int *pregnum)
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{
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int regnum;
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char *endptr = NULL;
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if (!*numstr) {
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return false;
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}
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regnum = strtoul(numstr, &endptr, 10);
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if (*endptr || (regnum >= maxnum)) {
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return false;
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}
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*pregnum = regnum;
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return true;
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}
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int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)
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{
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int i, regnum;
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CPUPPCState *env = cpu_env(cs);
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/* General purpose registers */
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if ((qemu_tolower(name[0]) == 'r') &&
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ppc_cpu_get_reg_num(name + 1, ARRAY_SIZE(env->gpr), ®num)) {
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*pval = env->gpr[regnum];
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return 0;
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}
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/* Floating point registers */
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if ((qemu_tolower(name[0]) == 'f') &&
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ppc_cpu_get_reg_num(name + 1, 32, ®num)) {
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*pval = *cpu_fpr_ptr(env, regnum);
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return 0;
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}
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/* Special purpose registers */
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for (i = 0; i < ARRAY_SIZE(env->spr_cb); ++i) {
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ppc_spr_t *spr = &env->spr_cb[i];
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if (spr->name && (strcasecmp(name, spr->name) == 0)) {
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*pval = env->spr[i];
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return 0;
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}
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}
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/* Segment registers */
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#if !defined(CONFIG_USER_ONLY)
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if ((strncasecmp(name, "sr", 2) == 0) &&
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ppc_cpu_get_reg_num(name + 2, ARRAY_SIZE(env->sr), ®num)) {
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*pval = env->sr[regnum];
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return 0;
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}
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#endif
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return -EINVAL;
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}
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CpuModelExpansionInfo *
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qmp_query_cpu_model_expansion(CpuModelExpansionType type,
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CpuModelInfo *model,
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Error **errp)
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{
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error_setg(errp, "CPU model expansion is not supported on this target");
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return NULL;
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}
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static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
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{
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ObjectClass *oc = data;
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CpuDefinitionInfoList **first = user_data;
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const char *typename;
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CpuDefinitionInfo *info;
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typename = object_class_get_name(oc);
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info = g_malloc0(sizeof(*info));
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info->name = cpu_model_from_type(typename);
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QAPI_LIST_PREPEND(*first, info);
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}
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CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
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{
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CpuDefinitionInfoList *cpu_list = NULL;
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GSList *list;
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int i;
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list = object_class_get_list(TYPE_POWERPC_CPU, false);
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g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
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g_slist_free(list);
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for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
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PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
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ObjectClass *oc;
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CpuDefinitionInfo *info;
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oc = ppc_cpu_class_by_name(alias->model);
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if (oc == NULL) {
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continue;
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}
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info = g_malloc0(sizeof(*info));
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info->name = g_strdup(alias->alias);
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info->q_typename = g_strdup(object_class_get_name(oc));
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QAPI_LIST_PREPEND(cpu_list, info);
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}
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return cpu_list;
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}
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