ddd8f3baa2
Create a QMP command to be used for generic ACPI APEI hardware error
injection (HEST) via GHESv2, and add support for it for ARM guests.
Error injection uses ACPI_HEST_SRC_ID_QMP source ID to be platform
independent. This is mapped at arch virt bindings, depending on the
types supported by QEMU and by the BIOS. So, on ARM, this is supported
via ACPI_GHES_NOTIFY_GPIO notification type.
This patch was co-authored:
- original ghes logic to inject a simple ARM record by Shiju Jose;
- generic logic to handle block addresses by Jonathan Cameron;
- generic GHESv2 error inject by Mauro Carvalho Chehab;
Co-authored-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Co-authored-by: Shiju Jose <shiju.jose@huawei.com>
Co-authored-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-ID: <81e2118b3c8b7e5da341817f277d61251655e0db.1758610789.git.mchehab+huawei@kernel.org>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
219 lines
6 KiB
C
219 lines
6 KiB
C
/*
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*
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* Copyright (c) 2015 Linaro Limited
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Emulate a virtual board which works by passing Linux all the information
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* it needs about what devices are present via the device tree.
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* There are some restrictions about what we can do here:
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* + we can only present devices whose Linux drivers will work based
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* purely on the device tree with no platform data at all
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* + we want to present a very stripped-down minimalist platform,
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* both because this reduces the security attack surface from the guest
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* and also because it reduces our exposure to being broken when
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* the kernel updates its device tree bindings and requires further
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* information in a device binding that we aren't providing.
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* This is essentially the same approach kvmtool uses.
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*/
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#ifndef QEMU_ARM_VIRT_H
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#define QEMU_ARM_VIRT_H
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#include "exec/hwaddr.h"
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#include "qemu/notify.h"
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#include "hw/boards.h"
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#include "hw/acpi/ghes.h"
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#include "hw/arm/boot.h"
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#include "hw/arm/bsa.h"
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#include "hw/block/flash.h"
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#include "hw/cxl/cxl.h"
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#include "system/kvm.h"
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#include "hw/intc/arm_gicv3_common.h"
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#include "qom/object.h"
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#define NUM_GICV2M_SPIS 64
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#define NUM_VIRTIO_TRANSPORTS 32
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#define NUM_SMMU_IRQS 4
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/* See Linux kernel arch/arm64/include/asm/pvclock-abi.h */
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#define PVTIME_SIZE_PER_CPU 64
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/* GPIO pins */
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#define GPIO_PIN_POWER_BUTTON 3
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enum {
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VIRT_FLASH,
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VIRT_MEM,
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VIRT_CPUPERIPHS,
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VIRT_GIC_DIST,
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VIRT_GIC_CPU,
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VIRT_GIC_V2M,
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VIRT_GIC_HYP,
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VIRT_GIC_VCPU,
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VIRT_GIC_ITS,
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VIRT_GIC_REDIST,
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VIRT_SMMU,
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VIRT_UART0,
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VIRT_MMIO,
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VIRT_RTC,
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VIRT_FW_CFG,
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VIRT_PCIE,
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VIRT_PCIE_MMIO,
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VIRT_PCIE_PIO,
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VIRT_PCIE_ECAM,
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VIRT_PLATFORM_BUS,
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VIRT_GPIO,
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VIRT_UART1,
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VIRT_SECURE_MEM,
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VIRT_SECURE_GPIO,
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VIRT_PCDIMM_ACPI,
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VIRT_ACPI_GED,
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VIRT_NVDIMM_ACPI,
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VIRT_PVTIME,
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VIRT_ACPI_PCIHP,
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VIRT_LOWMEMMAP_LAST,
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};
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/* indices of IO regions located after the RAM */
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enum {
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VIRT_HIGH_GIC_REDIST2 = VIRT_LOWMEMMAP_LAST,
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VIRT_CXL_HOST,
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VIRT_HIGH_PCIE_ECAM,
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VIRT_HIGH_PCIE_MMIO,
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};
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typedef enum VirtIOMMUType {
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VIRT_IOMMU_NONE,
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VIRT_IOMMU_SMMUV3,
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VIRT_IOMMU_VIRTIO,
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} VirtIOMMUType;
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typedef enum VirtMSIControllerType {
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VIRT_MSI_CTRL_NONE,
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VIRT_MSI_CTRL_GICV2M,
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VIRT_MSI_CTRL_ITS,
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} VirtMSIControllerType;
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typedef enum VirtGICType {
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VIRT_GIC_VERSION_MAX = 0,
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VIRT_GIC_VERSION_HOST = 1,
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/* The concrete GIC values have to match the GIC version number */
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VIRT_GIC_VERSION_2 = 2,
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VIRT_GIC_VERSION_3 = 3,
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VIRT_GIC_VERSION_4 = 4,
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VIRT_GIC_VERSION_NOSEL,
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} VirtGICType;
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#define VIRT_GIC_VERSION_2_MASK BIT(VIRT_GIC_VERSION_2)
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#define VIRT_GIC_VERSION_3_MASK BIT(VIRT_GIC_VERSION_3)
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#define VIRT_GIC_VERSION_4_MASK BIT(VIRT_GIC_VERSION_4)
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struct VirtMachineClass {
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MachineClass parent;
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bool no_tcg_its;
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bool no_highmem_compact;
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bool no_ged; /* Machines < 4.2 have no support for ACPI GED device */
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bool kvm_no_adjvtime;
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bool no_kvm_steal_time;
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bool acpi_expose_flash;
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bool no_secure_gpio;
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/* Machines < 6.2 have no support for describing cpu topology to guest */
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bool no_cpu_topology;
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bool no_tcg_lpa2;
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bool no_ns_el2_virt_timer_irq;
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bool no_nested_smmu;
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};
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struct VirtMachineState {
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MachineState parent;
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Notifier machine_done;
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DeviceState *platform_bus_dev;
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FWCfgState *fw_cfg;
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PFlashCFI01 *flash[2];
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bool secure;
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bool highmem;
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bool highmem_compact;
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bool highmem_cxl;
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bool highmem_ecam;
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bool highmem_mmio;
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bool highmem_redists;
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bool its;
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bool tcg_its;
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bool virt;
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bool ras;
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bool mte;
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bool dtb_randomness;
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bool second_ns_uart_present;
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OnOffAuto acpi;
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VirtGICType gic_version;
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VirtIOMMUType iommu;
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bool default_bus_bypass_iommu;
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VirtMSIControllerType msi_controller;
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uint16_t virtio_iommu_bdf;
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struct arm_boot_info bootinfo;
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MemMapEntry *memmap;
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char *pciehb_nodename;
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const int *irqmap;
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int fdt_size;
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uint32_t clock_phandle;
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uint32_t gic_phandle;
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uint32_t msi_phandle;
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uint32_t iommu_phandle;
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int psci_conduit;
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hwaddr highest_gpa;
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DeviceState *gic;
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DeviceState *acpi_dev;
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Notifier powerdown_notifier;
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Notifier generic_error_notifier;
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PCIBus *bus;
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char *oem_id;
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char *oem_table_id;
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bool ns_el2_virt_timer_irq;
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CXLState cxl_devices_state;
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bool legacy_smmuv3_present;
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};
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#define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)
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#define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
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OBJECT_DECLARE_TYPE(VirtMachineState, VirtMachineClass, VIRT_MACHINE)
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void virt_acpi_setup(VirtMachineState *vms);
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bool virt_is_acpi_enabled(VirtMachineState *vms);
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/* Return number of redistributors that fit in the specified region */
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static uint32_t virt_redist_capacity(VirtMachineState *vms, int region)
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{
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uint32_t redist_size;
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if (vms->gic_version == VIRT_GIC_VERSION_3) {
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redist_size = GICV3_REDIST_SIZE;
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} else {
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redist_size = GICV4_REDIST_SIZE;
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}
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return vms->memmap[region].size / redist_size;
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}
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/* Return the number of used redistributor regions */
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static inline int virt_gicv3_redist_region_count(VirtMachineState *vms)
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{
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uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST);
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assert(vms->gic_version != VIRT_GIC_VERSION_2);
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return (MACHINE(vms)->smp.cpus > redist0_capacity &&
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vms->highmem_redists) ? 2 : 1;
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}
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#endif /* QEMU_ARM_VIRT_H */
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