Peter Maydell e42c4db3a3 target-arm: Implement TTBCR changes for LPAE ... Implement the changes to the TTBCR register required for LPAE: * many fewer bits should be RAZ/WI * since TTBCR changes can result in a change of ASID, we must flush the TLB on writes to it Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2012-07-12 10:59:54 +00:00
..
arm-semi.c	build: move obj-TARGET-y variables to nested Makefile.objs	2012-06-07 07:17:36 +02:00
cpu-qom.h	target-arm: Convert cp15 crn=1 registers	2012-06-20 12:08:22 +00:00
cpu.c	target-arm: Extend feature flags to 64 bits	2012-07-12 10:59:54 +00:00
cpu.h	target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAE	2012-07-12 10:59:54 +00:00
helper.c	target-arm: Implement TTBCR changes for LPAE	2012-07-12 10:59:54 +00:00
helper.h	target-arm: Remove remaining old cp15 infrastructure	2012-06-20 12:13:04 +00:00
iwmmxt_helper.c	target-arm: Don't overuse CPUState	2012-03-14 22:20:24 +01:00
machine.c	target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAE	2012-07-12 10:59:54 +00:00
Makefile.objs	build: move other target-*/ objects to nested Makefile.objs	2012-06-07 09:21:11 +02:00
neon_helper.c	target-arm: When setting FPSCR.QC, don't clear other FPSCR bits	2012-05-10 12:56:08 +00:00
op_addsub.h	Correct spelling of licensed	2011-07-23 11:26:12 -05:00
op_helper.c	target-arm: initial coprocessor register framework	2012-06-20 12:01:02 +00:00
translate.c	target-arm: Fix TCG temp handling in 64 bit cp writes	2012-07-12 10:59:53 +00:00