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qemu-cr16/include/hw/riscv
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Alistair Francis ef63100648 hw/riscv: opentitan: Update to the latest build 
Update the OpenTitan machine model to match the latest OpenTitan FPGA
design.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 18b1b681b0f8dd2461e819d1217bf0b530812680.1634524691.git.alistair.francis@wdc.com
2021-10-22 23:35:47 +10:00
..
boot.h hw/riscv: Use macros for BIOS image names 2021-06-08 09:59:42 +10:00
boot_opensbi.h riscv: Add opensbi firmware dynamic support 2020-07-13 17:25:37 -07:00
microchip_pfsoc.h hw/riscv: microchip_pfsoc: Map EMMC/SD mux register 2021-03-22 21:54:40 -04:00
numa.h hw/riscv: Add helpers for RISC-V multi-socket NUMA machines 2020-08-25 09:11:35 -07:00
opentitan.h hw/riscv: opentitan: Update to the latest build 2021-10-22 23:35:47 +10:00
riscv_hart.h Use OBJECT_DECLARE_SIMPLE_TYPE when possible 2020-09-18 14:12:32 -04:00
shakti_c.h hw/riscv: Connect Shakti UART to Shakti platform 2021-05-11 20:02:06 +10:00
sifive_cpu.h riscv: Add a sifive_cpu.h to include both E and U cpu type defines 2019-09-17 08:42:46 -07:00
sifive_e.h sifive_e: Rename memmap enum constants 2020-09-18 13:49:48 -04:00
sifive_u.h sifive_u: Connect the SiFive PWM device 2021-09-21 07:56:49 +10:00
spike.h riscv: spike: Remove target macro conditionals 2020-12-17 21:56:44 -08:00
virt.h hw/riscv: virt: Add optional ACLINT support to virt machine 2021-09-21 07:56:49 +10:00