qemu-cr16/target
Chuang Xu f985a1195b i386/cpu: Fix number of addressable IDs field for CPUID.01H.EBX[23:16]
When QEMU is started with:
-cpu host,migratable=on,host-cache-info=on,l3-cache=off
-smp 180,sockets=2,dies=1,cores=45,threads=2

On Intel platform:
CPUID.01H.EBX[23:16] is defined as "max number of addressable IDs for
logical processors in the physical package".

When executing "cpuid -1 -l 1 -r" in the guest, we obtain a value of 90 for
CPUID.01H.EBX[23:16], whereas the expected value is 128. Additionally,
executing "cpuid -1 -l 4 -r" in the guest yields a value of 63 for
CPUID.04H.EAX[31:26], which matches the expected result.

As (1+CPUID.04H.EAX[31:26]) rounds up to the nearest power-of-2 integer,
it's necessary to round up CPUID.01H.EBX[23:16] to the nearest power-of-2
integer too. Otherwise there would be unexpected results in guest with
older kernel.

For example, when QEMU is started with CLI above and xtopology is disabled,
guest kernel 5.15.120 uses CPUID.01H.EBX[23:16]/(1+CPUID.04H.EAX[31:26]) to
calculate threads-per-core in detect_ht(). Then guest will get "90/(1+63)=1"
as the result, even though threads-per-core should actually be 2.

And on AMD platform:
CPUID.01H.EBX[23:16] is defined as "Logical processor count". Current
result meets our expectation.

So round up CPUID.01H.EBX[23:16] to the nearest power-of-2 integer only
for Intel platform to solve the unexpected result.

Use the "x-vendor-cpuid-only-v2" compat option to fix this issue.

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Guixiong Wei <weiguixiong@bytedance.com>
Signed-off-by: Yipeng Yin <yinyipeng@bytedance.com>
Signed-off-by: Chuang Xu <xuchuangxclwt@bytedance.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250714080859.1960104-5-zhao1.liu@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-07-14 10:29:17 +02:00
..
alpha target: Use cpu_pointer_wrap_notreached for strict align targets 2025-05-28 08:08:47 +01:00
arm target-arm queue: 2025-07-07 09:22:41 -04:00
avr target: Use cpu_pointer_wrap_uint32 for 32-bit targets 2025-05-28 08:08:48 +01:00
hexagon accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
hppa target: Use cpu_pointer_wrap_notreached for strict align targets 2025-05-28 08:08:47 +01:00
i386 i386/cpu: Fix number of addressable IDs field for CPUID.01H.EBX[23:16] 2025-07-14 10:29:17 +02:00
loongarch treewide: fix paths for relocated files in comments 2025-07-02 18:26:27 +02:00
m68k target: Use cpu_pointer_wrap_uint32 for 32-bit targets 2025-05-28 08:08:48 +01:00
microblaze target: Use cpu_pointer_wrap_uint32 for 32-bit targets 2025-05-28 08:08:48 +01:00
mips * target/i386/kvm: Intel TDX support 2025-05-30 11:41:07 -04:00
openrisc target: Use cpu_pointer_wrap_uint32 for 32-bit targets 2025-05-28 08:08:48 +01:00
ppc * target/i386/kvm: Intel TDX support 2025-05-30 11:41:07 -04:00
riscv target: riscv: Add Svrsw60t59b extension support 2025-07-04 21:09:49 +10:00
rx target: Use cpu_pointer_wrap_uint32 for 32-bit targets 2025-05-28 08:08:48 +01:00
s390x target/s390x: A fix for the trouble with tribles 2025-07-02 18:29:57 +02:00
sh4 target: Use cpu_pointer_wrap_notreached for strict align targets 2025-05-28 08:08:47 +01:00
sparc accel/tcg: Fix atomic_mmu_lookup vs TLB_FORCE_SLOW 2025-05-28 15:17:25 -04:00
tricore target: Use cpu_pointer_wrap_uint32 for 32-bit targets 2025-05-28 08:08:48 +01:00
xtensa target/xtensa: replace FSF postal address with licenses URL 2025-06-26 00:42:37 +02:00
Kconfig target/cris: Remove the deprecated CRIS target 2024-09-13 20:11:13 +02:00
meson.build target/cris: Remove the deprecated CRIS target 2024-09-13 20:11:13 +02:00