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wip! implement LPR(D), SPR(D) (stubs only)

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fridtjof 2025-08-15 01:35:35 +02:00
parent 31a4ca9d2c
commit 2b96aa2f41
2 changed files with 38 additions and 0 deletions
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18
target/cr16c/insn.decode
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@ -442,3 +442,21 @@ LOADM 0000 0000 1010 0... pair=0 @ldstm
LOADM 0000 0000 1010 1... pair=1 @ldstm
STORM 0000 0000 1011 0... pair=0 @ldstm
STORM 0000 0000 1011 1... pair=1 @ldstm
# Processor Register Manipulation
#LPR Rsrc, Rproc Load processor register
#LPRD RPsrc, Rprocd Load double processor register
#SPR Rproc, Rdest Store processor register
#SPRD Rprocd, RPdest Store double processor register
# fmt escape2
# followed by another word p4_4(mode) p3_4(res) p2_4(pr) p1_4(reg)
&lp_sp p2 p1
@lp_sp .... .... .... .... .... .... p2:4 p1:4 &lp_sp
# ope
LPR 0000 0000 0001 0100 0000 0000 .... .... @lp_sp
LPRD 0000 0000 0001 0100 0001 0000 .... .... @lp_sp
SPR 0000 0000 0001 0100 0010 0000 .... .... @lp_sp
SPRD 0000 0000 0001 0100 0011 0000 .... .... @lp_sp

20
target/cr16c/translate.c
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@ -1482,6 +1482,26 @@ static bool trans_STORM(DisasContext *ctx, arg_STORM *a) {
return true;
}
static bool trans_LPR(DisasContext *ctx, arg_LPR* a) {
gen_helper_raise_unimplemented_instruction();
return true;
}
static bool trans_LPRD(DisasContext *ctx, arg_LPRD* a) {
gen_helper_raise_unimplemented_instruction();
return true;
}
static bool trans_SPR(DisasContext *ctx, arg_SPR* a) {
gen_helper_raise_unimplemented_instruction();
return true;
}
static bool trans_SPRD(DisasContext *ctx, arg_SPRD* a) {
gen_helper_raise_unimplemented_instruction();
return true;
}
static bool trans_BAL_ra(DisasContext *ctx, arg_BAL_ra *a) {
#define BAL_LEN 4
// TODO BAL_rp would be 3 words/6 bytes (fmt 3a)