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target/arm: Reorder ENCODE_AA64_CP_REG arguments

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The order of the parameters in the Arm ARM is

  op0, op1, crn, crm, op2

Reorder the arguments of ENCODE_AA64_CP_REG to match.

Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2025-09-16 07:22:20 -07:00 • committed by Peter Maydell
parent 304ca4b827
commit 398a33aeda
4 changed files with 8 additions and 8 deletions
Download patch file Download diff file Expand all files Collapse all files

2
target/arm/cpregs.h
View file

@ -187,7 +187,7 @@ enum {
((is64) << CP_REG_AA32_64BIT_SHIFT) | \
((cp) << 16) | ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
#define ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2) \
#define ENCODE_AA64_CP_REG(op0, op1, crn, crm, op2) \
(CP_REG_AA64_MASK | CP_REG_ARM64_SYSREG | \
((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \

4
target/arm/helper.c
View file

@ -4503,7 +4503,7 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
};
#define K(op0, op1, crn, crm, op2) \
ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2)
ENCODE_AA64_CP_REG(op0, op1, crn, crm, op2)
static const struct E2HAlias aliases[] = {
{ K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
@ -7398,7 +7398,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
*/
assert(cp == 0 || r->state == ARM_CP_STATE_BOTH);
cp = 0;
key = ENCODE_AA64_CP_REG(r->crn, crm, r->opc0, opc1, opc2);
key = ENCODE_AA64_CP_REG(r->opc0, opc1, r->crn, crm, opc2);
break;
default:
g_assert_not_reached();

6
target/arm/hvf/hvf.c
View file

@ -1124,10 +1124,10 @@ static bool is_id_sysreg(uint32_t reg)
static uint32_t hvf_reg2cp_reg(uint32_t reg)
{
return ENCODE_AA64_CP_REG((reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK,
(reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK,
(reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK,
return ENCODE_AA64_CP_REG((reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK,
(reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK,
(reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK,
(reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK,
(reg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK);
}

4
target/arm/tcg/translate-a64.c
View file

@ -2466,7 +2466,7 @@ static void handle_sys(DisasContext *s, bool isread,
unsigned int op0, unsigned int op1, unsigned int op2,
unsigned int crn, unsigned int crm, unsigned int rt)
{
uint32_t key = ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2);
uint32_t key = ENCODE_AA64_CP_REG(op0, op1, crn, crm, op2);
const ARMCPRegInfo *ri = get_arm_cp_reginfo(s->cp_regs, key);
bool need_exit_tb = false;
bool nv_trap_to_el2 = false;
@ -2602,7 +2602,7 @@ static void handle_sys(DisasContext *s, bool isread,
* We don't use the EL1 register's access function, and
* fine-grained-traps on EL1 also do not apply here.
*/
key = ENCODE_AA64_CP_REG(crn, crm, op0, 0, op2);
key = ENCODE_AA64_CP_REG(op0, 0, crn, crm, op2);
ri = get_arm_cp_reginfo(s->cp_regs, key);
assert(ri);
assert(cp_access_ok(s->current_el, ri, isread));