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Various patches related to single binary work:

Browse source 
- Remove some VMSTATE_UINTTL() uses
 - Replace target_ulong by vaddr / hwaddr / uint[32,64]_t
 - Expand TCGv to TCGv_i32 for 32-bit targets
 - Remove some unnecessary checks on TARGET_LONG_BITS
 - Replace few HOST_BIG_ENDIAN preprocessor #ifdef by compile-time if() check
 - Expand MO_TE to either MO_BE or MO_LE
 
 Also:
 
 - Remove legacy cpu_physical_memory_*() calls
 - Fix HPPA FMPYADD opcode
 - Unify Clément Mathieu--Drif email addresses
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 =M9X9
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Merge tag 'single-binary-20251016' of https://github.com/philmd/qemu into staging

Various patches related to single binary work:

- Remove some VMSTATE_UINTTL() uses
- Replace target_ulong by vaddr / hwaddr / uint[32,64]_t
- Expand TCGv to TCGv_i32 for 32-bit targets
- Remove some unnecessary checks on TARGET_LONG_BITS
- Replace few HOST_BIG_ENDIAN preprocessor #ifdef by compile-time if() check
- Expand MO_TE to either MO_BE or MO_LE

Also:

- Remove legacy cpu_physical_memory_*() calls
- Fix HPPA FMPYADD opcode
- Unify Clément Mathieu--Drif email addresses

# -----BEGIN PGP SIGNATURE-----
#
# iQIyBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmjxCqIACgkQ4+MsLN6t
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# mRgeCHD1E0WBDsVV9yi9TnbzDF6SfNZP9XYcSHomrNt9qY0xcQ==
# =M9X9
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 16 Oct 2025 08:09:22 AM PDT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'single-binary-20251016' of https://github.com/philmd/qemu: (79 commits)
  mailmap: Unify Clément Mathieu--Drif emails
  linux-user/microblaze: Fix little-endianness binary
  target/xtensa: Remove target_ulong use in xtensa_get_tb_cpu_state()
  target/xtensa: Remove target_ulong use in xtensa_tr_translate_insn()
  target/xtensa: Replace legacy cpu_physical_memory_[un]map() calls
  target/tricore: Expand TCGv type for 32-bit target
  target/tricore: Un-inline various helpers
  target/tricore: Pass DisasContext as first argument
  target/tricore: Expand TCG helpers for 32-bit target
  target/tricore: Inline tcg_gen_ld32u_tl()
  target/tricore: Declare registers as TCGv_i32
  target/tricore: Replace target_ulong -> uint32_t in op_helper.c
  target/tricore: Remove unnecessary cast to target_ulong
  target/tricore: Remove target_ulong use in gen_addi_d()
  target/tricore: Remove target_ulong use in translate_insn() handler
  target/tricore: Replace target_ulong -> vaddr with tlb_fill() callees
  target/tricore: Remove target_ulong use in gen_goto_tb()
  target/sparc: Reduce inclusions of 'exec/cpu-common.h'
  target/sh4: Remove target_ulong use in gen_goto_tb()
  target/sh4: Use vaddr type for TLB virtual addresses
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-10-16 12:26:50 -07:00
commit 3ad3326bd6
66 changed files with 2925 additions and 2888 deletions
Download patch file Download diff file Expand all files Collapse all files

1
.mailmap
View file

@ -136,6 +136,7 @@ Chen Gang <gang.chen.5i5j@gmail.com>
Chen Gang <gang.chen@sunrus.com.cn>
Chen Wei-Ren <chenwj@iis.sinica.edu.tw>
Christophe Lyon <christophe.lyon@st.com>
Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Collin L. Walling <walling@linux.ibm.com>
Daniel P. Berrangé <berrange@redhat.com>
Eduardo Otubo <otubo@redhat.com>

3
linux-user/microblaze/elfload.c
View file

@ -8,7 +8,8 @@
const char *get_elf_cpu_model(uint32_t eflags)
{
return "any";
return TARGET_BIG_ENDIAN ? "any,little-endian=off"
: "any,little-endian=on";
}
void elf_core_copy_regs(target_elf_gregset_t *r, const CPUMBState *env)

1
target/alpha/helper.h
View file

@ -92,6 +92,7 @@ DEF_HELPER_FLAGS_1(tbia, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_2(tbis, TCG_CALL_NO_RWG, void, env, i64)
DEF_HELPER_1(halt, void, i64)
DEF_HELPER_1(whami, i64, env)
DEF_HELPER_FLAGS_0(get_vmtime, TCG_CALL_NO_RWG, i64)
DEF_HELPER_FLAGS_0(get_walltime, TCG_CALL_NO_RWG, i64)

34
target/alpha/machine.c
View file

@ -25,8 +25,8 @@ static const VMStateInfo vmstate_fpcr = {
};
static const VMStateField vmstate_env_fields[] = {
VMSTATE_UINTTL_ARRAY(ir, CPUAlphaState, 31),
VMSTATE_UINTTL_ARRAY(fir, CPUAlphaState, 31),
VMSTATE_UINT64_ARRAY(ir, CPUAlphaState, 31),
VMSTATE_UINT64_ARRAY(fir, CPUAlphaState, 31),
/* Save the architecture value of the fpcr, not the internally
expanded version. Since this architecture value does not
exist in memory to be stored, this requires a but of hoop
@ -41,27 +41,27 @@ static const VMStateField vmstate_env_fields[] = {
.flags = VMS_SINGLE,
.offset = 0
},
VMSTATE_UINTTL(pc, CPUAlphaState),
VMSTATE_UINTTL(unique, CPUAlphaState),
VMSTATE_UINTTL(lock_addr, CPUAlphaState),
VMSTATE_UINTTL(lock_value, CPUAlphaState),
VMSTATE_UINT64(pc, CPUAlphaState),
VMSTATE_UINT64(unique, CPUAlphaState),
VMSTATE_UINT64(lock_addr, CPUAlphaState),
VMSTATE_UINT64(lock_value, CPUAlphaState),
VMSTATE_UINT32(flags, CPUAlphaState),
VMSTATE_UINT32(pcc_ofs, CPUAlphaState),
VMSTATE_UINTTL(trap_arg0, CPUAlphaState),
VMSTATE_UINTTL(trap_arg1, CPUAlphaState),
VMSTATE_UINTTL(trap_arg2, CPUAlphaState),
VMSTATE_UINT64(trap_arg0, CPUAlphaState),
VMSTATE_UINT64(trap_arg1, CPUAlphaState),
VMSTATE_UINT64(trap_arg2, CPUAlphaState),
VMSTATE_UINTTL(exc_addr, CPUAlphaState),
VMSTATE_UINTTL(palbr, CPUAlphaState),
VMSTATE_UINTTL(ptbr, CPUAlphaState),
VMSTATE_UINTTL(vptptr, CPUAlphaState),
VMSTATE_UINTTL(sysval, CPUAlphaState),
VMSTATE_UINTTL(usp, CPUAlphaState),
VMSTATE_UINT64(exc_addr, CPUAlphaState),
VMSTATE_UINT64(palbr, CPUAlphaState),
VMSTATE_UINT64(ptbr, CPUAlphaState),
VMSTATE_UINT64(vptptr, CPUAlphaState),
VMSTATE_UINT64(sysval, CPUAlphaState),
VMSTATE_UINT64(usp, CPUAlphaState),
VMSTATE_UINTTL_ARRAY(shadow, CPUAlphaState, 8),
VMSTATE_UINTTL_ARRAY(scratch, CPUAlphaState, 24),
VMSTATE_UINT64_ARRAY(shadow, CPUAlphaState, 8),
VMSTATE_UINT64_ARRAY(scratch, CPUAlphaState, 24),
VMSTATE_END_OF_LIST()
};

5
target/alpha/sys_helper.c
View file

@ -67,3 +67,8 @@ void helper_set_alarm(CPUAlphaState *env, uint64_t expire)
timer_del(cpu->alarm_timer);
}
}
uint64_t HELPER(whami)(CPUAlphaState *env)
{
return env_cpu(env)->cpu_index;
}

11
target/alpha/translate.c
View file

@ -436,18 +436,18 @@ static DisasJumpType gen_store_conditional(DisasContext *ctx, int ra, int rb,
return DISAS_NEXT;
}
static void gen_goto_tb(DisasContext *ctx, int idx, int32_t disp)
static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx, int32_t disp)
{
if (translator_use_goto_tb(&ctx->base, ctx->base.pc_next + disp)) {
/* With PCREL, PC must always be up-to-date. */
if (ctx->pcrel) {
gen_pc_disp(ctx, cpu_pc, disp);
tcg_gen_goto_tb(idx);
tcg_gen_goto_tb(tb_slot_idx);
} else {
tcg_gen_goto_tb(idx);
tcg_gen_goto_tb(tb_slot_idx);
gen_pc_disp(ctx, cpu_pc, disp);
}
tcg_gen_exit_tb(ctx->base.tb, idx);
tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx);
} else {
gen_pc_disp(ctx, cpu_pc, disp);
tcg_gen_lookup_and_goto_ptr();
@ -1126,8 +1126,7 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode)
break;
case 0x3C:
/* WHAMI */
tcg_gen_ld32s_i64(ctx->ir[IR_V0], tcg_env,
-offsetof(AlphaCPU, env) + offsetof(CPUState, cpu_index));
gen_helper_whami(ctx->ir[IR_V0], tcg_env);
break;
case 0x3E:

8
target/arm/tcg/translate-a64.c
View file

@ -528,7 +528,7 @@ static inline bool use_goto_tb(DisasContext *s, uint64_t dest)
return translator_use_goto_tb(&s->base, dest);
}
static void gen_goto_tb(DisasContext *s, int n, int64_t diff)
static void gen_goto_tb(DisasContext *s, unsigned tb_slot_idx, int64_t diff)
{
if (use_goto_tb(s, s->pc_curr + diff)) {
/*
@ -541,12 +541,12 @@ static void gen_goto_tb(DisasContext *s, int n, int64_t diff)
*/
if (tb_cflags(s->base.tb) & CF_PCREL) {
gen_a64_update_pc(s, diff);
tcg_gen_goto_tb(n);
tcg_gen_goto_tb(tb_slot_idx);
} else {
tcg_gen_goto_tb(n);
tcg_gen_goto_tb(tb_slot_idx);
gen_a64_update_pc(s, diff);
}
tcg_gen_exit_tb(s->base.tb, n);
tcg_gen_exit_tb(s->base.tb, tb_slot_idx);
s->base.is_jmp = DISAS_NORETURN;
} else {
gen_a64_update_pc(s, diff);

8
target/arm/tcg/translate.c
View file

@ -1310,7 +1310,7 @@ static void gen_goto_ptr(void)
* cpu_loop_exec. Any live exit_requests will be processed as we
* enter the next TB.
*/
static void gen_goto_tb(DisasContext *s, int n, target_long diff)
static void gen_goto_tb(DisasContext *s, unsigned tb_slot_idx, target_long diff)
{
if (translator_use_goto_tb(&s->base, s->pc_curr + diff)) {
/*
@ -1323,12 +1323,12 @@ static void gen_goto_tb(DisasContext *s, int n, target_long diff)
*/
if (tb_cflags(s->base.tb) & CF_PCREL) {
gen_update_pc(s, diff);
tcg_gen_goto_tb(n);
tcg_gen_goto_tb(tb_slot_idx);
} else {
tcg_gen_goto_tb(n);
tcg_gen_goto_tb(tb_slot_idx);
gen_update_pc(s, diff);
}
tcg_gen_exit_tb(s->base.tb, n);
tcg_gen_exit_tb(s->base.tb, tb_slot_idx);
} else {
gen_update_pc(s, diff);
gen_goto_ptr();

7
target/avr/translate.c
View file

@ -981,14 +981,15 @@ static void gen_pop_ret(DisasContext *ctx, TCGv ret)
}
}
static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx,
target_ulong dest)
{
const TranslationBlock *tb = ctx->base.tb;
if (translator_use_goto_tb(&ctx->base, dest)) {
tcg_gen_goto_tb(n);
tcg_gen_goto_tb(tb_slot_idx);
tcg_gen_movi_i32(cpu_pc, dest);
tcg_gen_exit_tb(tb, n);
tcg_gen_exit_tb(tb, tb_slot_idx);
} else {
tcg_gen_movi_i32(cpu_pc, dest);
tcg_gen_lookup_and_goto_ptr();

8
target/hexagon/translate.c
View file

@ -133,15 +133,15 @@ static bool use_goto_tb(DisasContext *ctx, target_ulong dest)
return translator_use_goto_tb(&ctx->base, dest);
}
static void gen_goto_tb(DisasContext *ctx, int idx, target_ulong dest, bool
move_to_pc)
static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx,
target_ulong dest, bool move_to_pc)
{
if (use_goto_tb(ctx, dest)) {
tcg_gen_goto_tb(idx);
tcg_gen_goto_tb(tb_slot_idx);
if (move_to_pc) {
tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], dest);
}
tcg_gen_exit_tb(ctx->base.tb, idx);
tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx);
} else {
if (move_to_pc) {
tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], dest);

10
target/hppa/cpu.h
View file

@ -187,7 +187,7 @@ typedef struct HPPATLBEntry {
struct HPPATLBEntry *unused_next;
};
target_ulong pa;
hwaddr pa;
unsigned entry_valid : 1;
@ -320,8 +320,8 @@ void hppa_translate_code(CPUState *cs, TranslationBlock *tb,
#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU
static inline target_ulong hppa_form_gva_mask(uint64_t gva_offset_mask,
uint64_t spc, target_ulong off)
static inline vaddr hppa_form_gva_mask(uint64_t gva_offset_mask,
uint64_t spc, target_ulong off)
{
#ifdef CONFIG_USER_ONLY
return off & gva_offset_mask;
@ -330,8 +330,8 @@ static inline target_ulong hppa_form_gva_mask(uint64_t gva_offset_mask,
#endif
}
static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc,
target_ulong off)
static inline vaddr hppa_form_gva(CPUHPPAState *env, uint64_t spc,
target_ulong off)
{
return hppa_form_gva_mask(env->gva_offset_mask, spc, off);
}

4
target/hppa/helper.c
View file

@ -148,8 +148,8 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags)
m = UINT32_MAX;
}
qemu_fprintf(f, "IA_F %08" PRIx64 ":%0*" PRIx64 " (" TARGET_FMT_lx ")\n"
"IA_B %08" PRIx64 ":%0*" PRIx64 " (" TARGET_FMT_lx ")\n",
qemu_fprintf(f, "IA_F %08" PRIx64 ":%0*" PRIx64 " (0x%" VADDR_PRIx ")\n"
"IA_B %08" PRIx64 ":%0*" PRIx64 " (0x%" VADDR_PRIx ")\n",
env->iasq_f >> 32, w, m & env->iaoq_f,
hppa_form_gva_mask(env->gva_offset_mask, env->iasq_f,
env->iaoq_f),

8
target/hppa/insns.decode
View file

@ -365,10 +365,10 @@ fstd 011100 ..... ..... .. ............1. @ldstim11
&mpyadd rm1 rm2 ta ra tm
@mpyadd ...... rm1:5 rm2:5 ta:5 ra:5 . tm:5 &mpyadd
fmpyadd_f 000110 ..... ..... ..... ..... 0 ..... @mpyadd
fmpyadd_d 000110 ..... ..... ..... ..... 1 ..... @mpyadd
fmpysub_f 100110 ..... ..... ..... ..... 0 ..... @mpyadd
fmpysub_d 100110 ..... ..... ..... ..... 1 ..... @mpyadd
fmpyadd_f 000110 ..... ..... ..... ..... 1 ..... @mpyadd
fmpyadd_d 000110 ..... ..... ..... ..... 0 ..... @mpyadd
fmpysub_f 100110 ..... ..... ..... ..... 1 ..... @mpyadd
fmpysub_d 100110 ..... ..... ..... ..... 0 ..... @mpyadd
####
# Conditional Branches

2
target/hppa/mem_helper.c
View file

@ -803,7 +803,7 @@ void HELPER(diag_btlb)(CPUHPPAState *env)
uint64_t HELPER(b_gate_priv)(CPUHPPAState *env, uint64_t iaoq_f)
{
uint64_t gva = hppa_form_gva(env, env->iasq_f, iaoq_f);
vaddr gva = hppa_form_gva(env, env->iasq_f, iaoq_f);
HPPATLBEntry *ent = hppa_find_tlb(env, gva);
if (ent == NULL) {

6
target/hppa/trace-events
View file

@ -1,13 +1,13 @@
# See docs/devel/tracing.rst for syntax documentation.
# mem_helper.c
disable hppa_tlb_flush_ent(void *env, void *ent, uint64_t va_b, uint64_t va_e, uint64_t pa) "env=%p ent=%p va_b=0x%lx va_e=0x%lx pa=0x%lx"
disable hppa_tlb_find_entry(void *env, void *ent, int valid, uint64_t va_b, uint64_t va_e, uint64_t pa) "env=%p ent=%p valid=%d va_b=0x%lx va_e=0x%lx pa=0x%lx"
disable hppa_tlb_flush_ent(void *env, void *ent, uint64_t va_b, uint64_t va_e, uint64_t pa) "env=%p ent=%p va_b=0x%lx va_e=0x%lx pa=0x%" PRIx64
disable hppa_tlb_find_entry(void *env, void *ent, int valid, uint64_t va_b, uint64_t va_e, uint64_t pa) "env=%p ent=%p valid=%d va_b=0x%lx va_e=0x%lx pa=0x%" PRIx64
disable hppa_tlb_find_entry_not_found(void *env, uint64_t addr) "env=%p addr=%08lx"
disable hppa_tlb_get_physical_address(void *env, int ret, int prot, uint64_t addr, uint64_t phys) "env=%p ret=%d prot=%d addr=0x%lx phys=0x%lx"
disable hppa_tlb_fill_excp(void *env, uint64_t addr, int size, int type, int mmu_idx) "env=%p addr=0x%lx size=%d type=%d mmu_idx=%d"
disable hppa_tlb_fill_success(void *env, uint64_t addr, uint64_t phys, int size, int type, int mmu_idx) "env=%p addr=0x%lx phys=0x%lx size=%d type=%d mmu_idx=%d"
disable hppa_tlb_itlba(void *env, void *ent, uint64_t va_b, uint64_t va_e, uint64_t pa) "env=%p ent=%p va_b=0x%lx va_e=0x%lx pa=0x%lx"
disable hppa_tlb_itlba(void *env, void *ent, uint64_t va_b, uint64_t va_e, uint64_t pa) "env=%p ent=%p va_b=0x%lx va_e=0x%lx pa=0x%" PRIx64
disable hppa_tlb_itlbp(void *env, void *ent, int access_id, int u, int pl2, int pl1, int type, int b, int d, int t) "env=%p ent=%p access_id=%x u=%d pl2=%d pl1=%d type=%d b=%d d=%d t=%d"
disable hppa_tlb_ptlb(void *env) "env=%p"
disable hppa_tlb_ptlb_local(void *env) "env=%p"

24
target/hppa/translate.c
View file

@ -104,6 +104,12 @@ typedef struct DisasContext {
#define MMU_DISABLED(C) MMU_IDX_MMU_DISABLED((C)->mmu_idx)
#endif
static inline MemOp mo_endian(DisasContext *ctx)
{
/* The PSW_E bit sets the (little) endianness, but we don't implement it. */
return MO_BE;
}
/* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */
static int expand_sm_imm(DisasContext *ctx, int val)
{
@ -1599,6 +1605,7 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb,
/* Caller uses nullify_over/nullify_end. */
assert(ctx->null_cond.c == TCG_COND_NEVER);
mop |= mo_endian(ctx);
form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
MMU_DISABLED(ctx));
tcg_gen_qemu_ld_i32(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
@ -1617,6 +1624,7 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb,
/* Caller uses nullify_over/nullify_end. */
assert(ctx->null_cond.c == TCG_COND_NEVER);
mop |= mo_endian(ctx);
form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
MMU_DISABLED(ctx));
tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
@ -1635,6 +1643,7 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb,
/* Caller uses nullify_over/nullify_end. */
assert(ctx->null_cond.c == TCG_COND_NEVER);
mop |= mo_endian(ctx);
form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
MMU_DISABLED(ctx));
tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
@ -1653,6 +1662,7 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb,
/* Caller uses nullify_over/nullify_end. */
assert(ctx->null_cond.c == TCG_COND_NEVER);
mop |= mo_endian(ctx);
form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
MMU_DISABLED(ctx));
tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
@ -1691,7 +1701,7 @@ static bool do_floadw(DisasContext *ctx, unsigned rt, unsigned rb,
nullify_over(ctx);
tmp = tcg_temp_new_i32();
do_load_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUL);
do_load_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_UL);
save_frw_i32(rt, tmp);
if (rt == 0) {
@ -1716,7 +1726,7 @@ static bool do_floadd(DisasContext *ctx, unsigned rt, unsigned rb,
nullify_over(ctx);
tmp = tcg_temp_new_i64();
do_load_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUQ);
do_load_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_UQ);
save_frd(rt, tmp);
if (rt == 0) {
@ -1750,7 +1760,7 @@ static bool do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb,
nullify_over(ctx);
tmp = load_frw_i32(rt);
do_store_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUL);
do_store_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_UL);
return nullify_end(ctx);
}
@ -1770,7 +1780,7 @@ static bool do_fstored(DisasContext *ctx, unsigned rt, unsigned rb,
nullify_over(ctx);
tmp = load_frd(rt);
do_store_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUQ);
do_store_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_UQ);
return nullify_end(ctx);
}
@ -3302,7 +3312,7 @@ static bool trans_ld(DisasContext *ctx, arg_ldst *a)
return gen_illegal(ctx);
}
return do_load(ctx, a->t, a->b, a->x, a->scale ? a->size : 0,
a->disp, a->sp, a->m, a->size | MO_TE);
a->disp, a->sp, a->m, a->size);
}
static bool trans_st(DisasContext *ctx, arg_ldst *a)
@ -3311,12 +3321,12 @@ static bool trans_st(DisasContext *ctx, arg_ldst *a)
if (!ctx->is_pa20 && a->size > MO_32) {
return gen_illegal(ctx);
}
return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size | MO_TE);
return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size);
}
static bool trans_ldc(DisasContext *ctx, arg_ldst *a)
{
MemOp mop = MO_TE | MO_ALIGN | a->size;
MemOp mop = mo_endian(ctx) | MO_ALIGN | a->size;
TCGv_i64 dest, ofs;
TCGv_i64 addr;

134
target/i386/monitor.c
View file

@ -30,6 +30,7 @@
#include "qobject/qdict.h"
#include "qapi/error.h"
#include "qapi/qapi-commands-misc.h"
#include "system/memory.h"
/* Perform linear address sign extension */
static hwaddr addr_canonical(CPUArchState *env, hwaddr addr)
@ -68,23 +69,23 @@ static void print_pte(Monitor *mon, CPUArchState *env, hwaddr addr,
pte & PG_RW_MASK ? 'W' : '-');
}
static void tlb_info_32(Monitor *mon, CPUArchState *env)
static void tlb_info_32(Monitor *mon, CPUArchState *env, AddressSpace *as)
{
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
unsigned int l1, l2;
uint32_t pgd, pde, pte;
pgd = env->cr[3] & ~0xfff;
for(l1 = 0; l1 < 1024; l1++) {
cpu_physical_memory_read(pgd + l1 * 4, &pde, 4);
pde = le32_to_cpu(pde);
pde = address_space_ldl_le(as, pgd + l1 * 4, attrs, NULL);
if (pde & PG_PRESENT_MASK) {
if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
/* 4M pages */
print_pte(mon, env, (l1 << 22), pde, ~((1 << 21) - 1));
} else {
for(l2 = 0; l2 < 1024; l2++) {
cpu_physical_memory_read((pde & ~0xfff) + l2 * 4, &pte, 4);
pte = le32_to_cpu(pte);
pte = address_space_ldl_le(as, (pde & ~0xfff) + l2 * 4,
attrs, NULL);
if (pte & PG_PRESENT_MASK) {
print_pte(mon, env, (l1 << 22) + (l2 << 12),
pte & ~PG_PSE_MASK,
@ -96,21 +97,20 @@ static void tlb_info_32(Monitor *mon, CPUArchState *env)
}
}
static void tlb_info_pae32(Monitor *mon, CPUArchState *env)
static void tlb_info_pae32(Monitor *mon, CPUArchState *env, AddressSpace *as)
{
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
unsigned int l1, l2, l3;
uint64_t pdpe, pde, pte;
uint64_t pdp_addr, pd_addr, pt_addr;
pdp_addr = env->cr[3] & ~0x1f;
for (l1 = 0; l1 < 4; l1++) {
cpu_physical_memory_read(pdp_addr + l1 * 8, &pdpe, 8);
pdpe = le64_to_cpu(pdpe);
pdpe = address_space_ldq_le(as, pdp_addr + l1 * 8, attrs, NULL);
if (pdpe & PG_PRESENT_MASK) {
pd_addr = pdpe & 0x3fffffffff000ULL;
for (l2 = 0; l2 < 512; l2++) {
cpu_physical_memory_read(pd_addr + l2 * 8, &pde, 8);
pde = le64_to_cpu(pde);
pde = address_space_ldq_le(as, pd_addr + l2 * 8, attrs, NULL);
if (pde & PG_PRESENT_MASK) {
if (pde & PG_PSE_MASK) {
/* 2M pages with PAE, CR4.PSE is ignored */
@ -119,8 +119,8 @@ static void tlb_info_pae32(Monitor *mon, CPUArchState *env)
} else {
pt_addr = pde & 0x3fffffffff000ULL;
for (l3 = 0; l3 < 512; l3++) {
cpu_physical_memory_read(pt_addr + l3 * 8, &pte, 8);
pte = le64_to_cpu(pte);
pte = address_space_ldq_le(as, pt_addr + l3 * 8,
attrs, NULL);
if (pte & PG_PRESENT_MASK) {
print_pte(mon, env, (l1 << 30) + (l2 << 21)
+ (l3 << 12),
@ -136,24 +136,23 @@ static void tlb_info_pae32(Monitor *mon, CPUArchState *env)
}
#ifdef TARGET_X86_64
static void tlb_info_la48(Monitor *mon, CPUArchState *env,
static void tlb_info_la48(Monitor *mon, CPUArchState *env, AddressSpace *as,
uint64_t l0, uint64_t pml4_addr)
{
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
uint64_t l1, l2, l3, l4;
uint64_t pml4e, pdpe, pde, pte;
uint64_t pdp_addr, pd_addr, pt_addr;
for (l1 = 0; l1 < 512; l1++) {
cpu_physical_memory_read(pml4_addr + l1 * 8, &pml4e, 8);
pml4e = le64_to_cpu(pml4e);
pml4e = address_space_ldq_le(as, pml4_addr + l1 * 8, attrs, NULL);
if (!(pml4e & PG_PRESENT_MASK)) {
continue;
}
pdp_addr = pml4e & 0x3fffffffff000ULL;
for (l2 = 0; l2 < 512; l2++) {
cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8);
pdpe = le64_to_cpu(pdpe);
pdpe = address_space_ldq_le(as, pdp_addr + l2 * 8, attrs, NULL);
if (!(pdpe & PG_PRESENT_MASK)) {
continue;
}
@ -167,8 +166,7 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *env,
pd_addr = pdpe & 0x3fffffffff000ULL;
for (l3 = 0; l3 < 512; l3++) {
cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8);
pde = le64_to_cpu(pde);
pde = address_space_ldq_le(as, pd_addr + l3 * 8, attrs, NULL);
if (!(pde & PG_PRESENT_MASK)) {
continue;
}
@ -182,10 +180,8 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *env,
pt_addr = pde & 0x3fffffffff000ULL;
for (l4 = 0; l4 < 512; l4++) {
cpu_physical_memory_read(pt_addr
+ l4 * 8,
&pte, 8);
pte = le64_to_cpu(pte);
pte = address_space_ldq_le(as, pt_addr + l4 * 8,
attrs, NULL);
if (pte & PG_PRESENT_MASK) {
print_pte(mon, env, (l0 << 48) + (l1 << 39) +
(l2 << 30) + (l3 << 21) + (l4 << 12),
@ -197,18 +193,18 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *env,
}
}
static void tlb_info_la57(Monitor *mon, CPUArchState *env)
static void tlb_info_la57(Monitor *mon, CPUArchState *env, AddressSpace *as)
{
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
uint64_t l0;
uint64_t pml5e;
uint64_t pml5_addr;
pml5_addr = env->cr[3] & 0x3fffffffff000ULL;
for (l0 = 0; l0 < 512; l0++) {
cpu_physical_memory_read(pml5_addr + l0 * 8, &pml5e, 8);
pml5e = le64_to_cpu(pml5e);
pml5e = address_space_ldq_le(as, pml5_addr + l0 * 8, attrs, NULL);
if (pml5e & PG_PRESENT_MASK) {
tlb_info_la48(mon, env, l0, pml5e & 0x3fffffffff000ULL);
tlb_info_la48(mon, env, as, l0, pml5e & 0x3fffffffff000ULL);
}
}
}
@ -217,6 +213,7 @@ static void tlb_info_la57(Monitor *mon, CPUArchState *env)
void hmp_info_tlb(Monitor *mon, const QDict *qdict)
{
CPUArchState *env;
AddressSpace *as;
env = mon_get_cpu_env(mon);
if (!env) {
@ -228,21 +225,22 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict)
monitor_printf(mon, "PG disabled\n");
return;
}
as = cpu_get_address_space(env_cpu(env), X86ASIdx_MEM);
if (env->cr[4] & CR4_PAE_MASK) {
#ifdef TARGET_X86_64
if (env->hflags & HF_LMA_MASK) {
if (env->cr[4] & CR4_LA57_MASK) {
tlb_info_la57(mon, env);
tlb_info_la57(mon, env, as);
} else {
tlb_info_la48(mon, env, 0, env->cr[3] & 0x3fffffffff000ULL);
tlb_info_la48(mon, env, as, 0, env->cr[3] & 0x3fffffffff000ULL);
}
} else
#endif
{
tlb_info_pae32(mon, env);
tlb_info_pae32(mon, env, as);
}
} else {
tlb_info_32(mon, env);
tlb_info_32(mon, env, as);
}
}
@ -271,8 +269,9 @@ static void mem_print(Monitor *mon, CPUArchState *env,
}
}
static void mem_info_32(Monitor *mon, CPUArchState *env)
static void mem_info_32(Monitor *mon, CPUArchState *env, AddressSpace *as)
{
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
unsigned int l1, l2;
int prot, last_prot;
uint32_t pgd, pde, pte;
@ -282,8 +281,7 @@ static void mem_info_32(Monitor *mon, CPUArchState *env)
last_prot = 0;
start = -1;
for(l1 = 0; l1 < 1024; l1++) {
cpu_physical_memory_read(pgd + l1 * 4, &pde, 4);
pde = le32_to_cpu(pde);
pde = address_space_ldl_le(as, pgd + l1 * 4, attrs, NULL);
end = l1 << 22;
if (pde & PG_PRESENT_MASK) {
if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
@ -291,8 +289,8 @@ static void mem_info_32(Monitor *mon, CPUArchState *env)
mem_print(mon, env, &start, &last_prot, end, prot);
} else {
for(l2 = 0; l2 < 1024; l2++) {
cpu_physical_memory_read((pde & ~0xfff) + l2 * 4, &pte, 4);
pte = le32_to_cpu(pte);
pte = address_space_ldl_le(as, (pde & ~0xfff) + l2 * 4,
attrs, NULL);
end = (l1 << 22) + (l2 << 12);
if (pte & PG_PRESENT_MASK) {
prot = pte & pde &
@ -312,8 +310,9 @@ static void mem_info_32(Monitor *mon, CPUArchState *env)
mem_print(mon, env, &start, &last_prot, (hwaddr)1 << 32, 0);
}
static void mem_info_pae32(Monitor *mon, CPUArchState *env)
static void mem_info_pae32(Monitor *mon, CPUArchState *env, AddressSpace *as)
{
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
unsigned int l1, l2, l3;
int prot, last_prot;
uint64_t pdpe, pde, pte;
@ -324,14 +323,12 @@ static void mem_info_pae32(Monitor *mon, CPUArchState *env)
last_prot = 0;
start = -1;
for (l1 = 0; l1 < 4; l1++) {
cpu_physical_memory_read(pdp_addr + l1 * 8, &pdpe, 8);
pdpe = le64_to_cpu(pdpe);
pdpe = address_space_ldq_le(as, pdp_addr + l1 * 8, attrs, NULL);
end = l1 << 30;
if (pdpe & PG_PRESENT_MASK) {
pd_addr = pdpe & 0x3fffffffff000ULL;
for (l2 = 0; l2 < 512; l2++) {
cpu_physical_memory_read(pd_addr + l2 * 8, &pde, 8);
pde = le64_to_cpu(pde);
pde = address_space_ldq_le(as, pd_addr + l2 * 8, attrs, NULL);
end = (l1 << 30) + (l2 << 21);
if (pde & PG_PRESENT_MASK) {
if (pde & PG_PSE_MASK) {
@ -341,8 +338,8 @@ static void mem_info_pae32(Monitor *mon, CPUArchState *env)
} else {
pt_addr = pde & 0x3fffffffff000ULL;
for (l3 = 0; l3 < 512; l3++) {
cpu_physical_memory_read(pt_addr + l3 * 8, &pte, 8);
pte = le64_to_cpu(pte);
pte = address_space_ldq_le(as, pt_addr + l3 * 8,
attrs, NULL);
end = (l1 << 30) + (l2 << 21) + (l3 << 12);
if (pte & PG_PRESENT_MASK) {
prot = pte & pde & (PG_USER_MASK | PG_RW_MASK |
@ -369,8 +366,9 @@ static void mem_info_pae32(Monitor *mon, CPUArchState *env)
#ifdef TARGET_X86_64
static void mem_info_la48(Monitor *mon, CPUArchState *env)
static void mem_info_la48(Monitor *mon, CPUArchState *env, AddressSpace *as)
{
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
int prot, last_prot;
uint64_t l1, l2, l3, l4;
uint64_t pml4e, pdpe, pde, pte;
@ -380,14 +378,12 @@ static void mem_info_la48(Monitor *mon, CPUArchState *env)
last_prot = 0;
start = -1;
for (l1 = 0; l1 < 512; l1++) {
cpu_physical_memory_read(pml4_addr + l1 * 8, &pml4e, 8);
pml4e = le64_to_cpu(pml4e);
pml4e = address_space_ldq_le(as, pml4_addr + l1 * 8, attrs, NULL);
end = l1 << 39;
if (pml4e & PG_PRESENT_MASK) {
pdp_addr = pml4e & 0x3fffffffff000ULL;
for (l2 = 0; l2 < 512; l2++) {
cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8);
pdpe = le64_to_cpu(pdpe);
pdpe = address_space_ldq_le(as, pdp_addr + l2 * 8, attrs, NULL);
end = (l1 << 39) + (l2 << 30);
if (pdpe & PG_PRESENT_MASK) {
if (pdpe & PG_PSE_MASK) {
@ -398,8 +394,8 @@ static void mem_info_la48(Monitor *mon, CPUArchState *env)
} else {
pd_addr = pdpe & 0x3fffffffff000ULL;
for (l3 = 0; l3 < 512; l3++) {
cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8);
pde = le64_to_cpu(pde);
pde = address_space_ldq_le(as, pd_addr + l3 * 8,
attrs, NULL);
end = (l1 << 39) + (l2 << 30) + (l3 << 21);
if (pde & PG_PRESENT_MASK) {
if (pde & PG_PSE_MASK) {
@ -411,10 +407,10 @@ static void mem_info_la48(Monitor *mon, CPUArchState *env)
} else {
pt_addr = pde & 0x3fffffffff000ULL;
for (l4 = 0; l4 < 512; l4++) {
cpu_physical_memory_read(pt_addr
+ l4 * 8,
&pte, 8);
pte = le64_to_cpu(pte);
pte = address_space_ldq_le(as,
pt_addr
+ l4 * 8,
attrs, NULL);
end = (l1 << 39) + (l2 << 30) +
(l3 << 21) + (l4 << 12);
if (pte & PG_PRESENT_MASK) {
@ -449,8 +445,9 @@ static void mem_info_la48(Monitor *mon, CPUArchState *env)
mem_print(mon, env, &start, &last_prot, (hwaddr)1 << 48, 0);
}
static void mem_info_la57(Monitor *mon, CPUArchState *env)
static void mem_info_la57(Monitor *mon, CPUArchState *env, AddressSpace *as)
{
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
int prot, last_prot;
uint64_t l0, l1, l2, l3, l4;
uint64_t pml5e, pml4e, pdpe, pde, pte;
@ -460,8 +457,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env)
last_prot = 0;
start = -1;
for (l0 = 0; l0 < 512; l0++) {
cpu_physical_memory_read(pml5_addr + l0 * 8, &pml5e, 8);
pml5e = le64_to_cpu(pml5e);
pml5e = address_space_ldq_le(as, pml5_addr + l0 * 8, attrs, NULL);
end = l0 << 48;
if (!(pml5e & PG_PRESENT_MASK)) {
prot = 0;
@ -471,8 +467,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env)
pml4_addr = pml5e & 0x3fffffffff000ULL;
for (l1 = 0; l1 < 512; l1++) {
cpu_physical_memory_read(pml4_addr + l1 * 8, &pml4e, 8);
pml4e = le64_to_cpu(pml4e);
pml4e = address_space_ldq_le(as, pml4_addr + l1 * 8, attrs, NULL);
end = (l0 << 48) + (l1 << 39);
if (!(pml4e & PG_PRESENT_MASK)) {
prot = 0;
@ -482,8 +477,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env)
pdp_addr = pml4e & 0x3fffffffff000ULL;
for (l2 = 0; l2 < 512; l2++) {
cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8);
pdpe = le64_to_cpu(pdpe);
pdpe = address_space_ldq_le(as, pdp_addr + l2 * 8, attrs, NULL);
end = (l0 << 48) + (l1 << 39) + (l2 << 30);
if (pdpe & PG_PRESENT_MASK) {
prot = 0;
@ -501,8 +495,8 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env)
pd_addr = pdpe & 0x3fffffffff000ULL;
for (l3 = 0; l3 < 512; l3++) {
cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8);
pde = le64_to_cpu(pde);
pde = address_space_ldq_le(as, pd_addr + l3 * 8,
attrs, NULL);
end = (l0 << 48) + (l1 << 39) + (l2 << 30) + (l3 << 21);
if (pde & PG_PRESENT_MASK) {
prot = 0;
@ -520,8 +514,8 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env)
pt_addr = pde & 0x3fffffffff000ULL;
for (l4 = 0; l4 < 512; l4++) {
cpu_physical_memory_read(pt_addr + l4 * 8, &pte, 8);
pte = le64_to_cpu(pte);
pte = address_space_ldq_le(as, pt_addr + l4 * 8,
attrs, NULL);
end = (l0 << 48) + (l1 << 39) + (l2 << 30) +
(l3 << 21) + (l4 << 12);
if (pte & PG_PRESENT_MASK) {
@ -545,6 +539,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env)
void hmp_info_mem(Monitor *mon, const QDict *qdict)
{
CPUArchState *env;
AddressSpace *as;
env = mon_get_cpu_env(mon);
if (!env) {
@ -556,21 +551,22 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
monitor_printf(mon, "PG disabled\n");
return;
}
as = cpu_get_address_space(env_cpu(env), X86ASIdx_MEM);
if (env->cr[4] & CR4_PAE_MASK) {
#ifdef TARGET_X86_64
if (env->hflags & HF_LMA_MASK) {
if (env->cr[4] & CR4_LA57_MASK) {
mem_info_la57(mon, env);
mem_info_la57(mon, env, as);
} else {
mem_info_la48(mon, env);
mem_info_la48(mon, env, as);
}
} else
#endif
{
mem_info_pae32(mon, env);
mem_info_pae32(mon, env, as);
}
} else {
mem_info_32(mon, env);
mem_info_32(mon, env, as);
}
}

2
target/loongarch/cpu-mmu.h
View file

@ -34,7 +34,7 @@ TLBRet get_physical_address(CPULoongArchState *env, MMUContext *context,
MMUAccessType access_type, int mmu_idx,
int is_debug);
void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
uint64_t *dir_width, target_ulong level);
uint64_t *dir_width, unsigned int level);
hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
#endif /* LOONGARCH_CPU_MMU_H */

2
target/loongarch/cpu_helper.c
View file

@ -17,7 +17,7 @@
#include "tcg/tcg_loongarch.h"
void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
uint64_t *dir_width, target_ulong level)
uint64_t *dir_width, unsigned int level)
{
switch (level) {
case 1:

2
target/loongarch/gdbstub.c
View file

@ -62,7 +62,7 @@ int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
CPULoongArchState *env = cpu_env(cs);
target_ulong tmp;
uint64_t tmp;
int length = 0;
if (n < 0 || n > 34) {

4
target/loongarch/machine.c
View file

@ -191,8 +191,8 @@ const VMStateDescription vmstate_loongarch_cpu = {
.version_id = 4,
.minimum_version_id = 4,
.fields = (const VMStateField[]) {
VMSTATE_UINTTL_ARRAY(env.gpr, LoongArchCPU, 32),
VMSTATE_UINTTL(env.pc, LoongArchCPU),
VMSTATE_UINT64_ARRAY(env.gpr, LoongArchCPU, 32),
VMSTATE_UINT64(env.pc, LoongArchCPU),
/* Remaining CSRs */
VMSTATE_UINT64(env.CSR_CRMD, LoongArchCPU),

2
target/loongarch/tcg/helper.h
View file

@ -129,7 +129,7 @@ DEF_HELPER_2(invtlb_all_asid, void, env, tl)
DEF_HELPER_3(invtlb_page_asid, void, env, tl, tl)
DEF_HELPER_3(invtlb_page_asid_or_g, void, env, tl, tl)
DEF_HELPER_4(lddir, tl, env, tl, tl, i32)
DEF_HELPER_4(lddir, tl, env, tl, i32, i32)
DEF_HELPER_4(ldpte, void, env, tl, tl, i32)
DEF_HELPER_1(ertn, void, env)
DEF_HELPER_1(idle, void, env)

2
target/loongarch/tcg/insn_trans/trans_privileged.c.inc
View file

@ -380,7 +380,7 @@ static bool trans_lddir(DisasContext *ctx, arg_lddir *a)
if (check_plv(ctx)) {
return false;
}
gen_helper_lddir(dest, tcg_env, src, tcg_constant_tl(a->imm), mem_idx);
gen_helper_lddir(dest, tcg_env, src, tcg_constant_i32(a->imm), mem_idx);
return true;
}

4
target/loongarch/tcg/tlb_helper.c
View file

@ -599,7 +599,7 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
}
target_ulong helper_lddir(CPULoongArchState *env, target_ulong base,
target_ulong level, uint32_t mem_idx)
uint32_t level, uint32_t mem_idx)
{
CPUState *cs = env_cpu(env);
target_ulong badvaddr, index, phys;
@ -607,7 +607,7 @@ target_ulong helper_lddir(CPULoongArchState *env, target_ulong base,
if (unlikely((level == 0) || (level > 4))) {
qemu_log_mask(LOG_GUEST_ERROR,
"Attepted LDDIR with level %"PRId64"\n", level);
"Attepted LDDIR with level %u\n", level);
return base;
}

6
target/loongarch/tcg/translate.c
View file

@ -99,16 +99,16 @@ void generate_exception(DisasContext *ctx, int excp)
ctx->base.is_jmp = DISAS_NORETURN;
}
static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx, vaddr dest)
{
if (ctx->va32) {
dest = (uint32_t) dest;
}
if (translator_use_goto_tb(&ctx->base, dest)) {
tcg_gen_goto_tb(n);
tcg_gen_goto_tb(tb_slot_idx);
tcg_gen_movi_tl(cpu_pc, dest);
tcg_gen_exit_tb(ctx->base.tb, n);
tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx);
} else {
tcg_gen_movi_tl(cpu_pc, dest);
tcg_gen_lookup_and_goto_ptr();

17
target/m68k/translate.c
View file

@ -44,9 +44,6 @@
#undef DEFO32
#undef DEFO64
static TCGv_i32 cpu_halted;
static TCGv_i32 cpu_exception_index;
static char cpu_reg_names[2 * 8 * 3 + 5 * 4];
static TCGv cpu_dregs[8];
static TCGv cpu_aregs[8];
@ -78,14 +75,6 @@ void m68k_tcg_init(void)
#undef DEFO32
#undef DEFO64
cpu_halted = tcg_global_mem_new_i32(tcg_env,
-offsetof(M68kCPU, env) +
offsetof(CPUState, halted), "HALTED");
cpu_exception_index = tcg_global_mem_new_i32(tcg_env,
-offsetof(M68kCPU, env) +
offsetof(CPUState, exception_index),
"EXCEPTION");
p = cpu_reg_names;
for (i = 0; i < 8; i++) {
sprintf(p, "D%d", i);
@ -4512,7 +4501,8 @@ DISAS_INSN(halt)
gen_exception(s, s->pc, EXCP_SEMIHOSTING);
return;
}
tcg_gen_movi_i32(cpu_halted, 1);
tcg_gen_st_i32(tcg_constant_i32(1), tcg_env,
offsetof(CPUState, halted) - offsetof(M68kCPU, env));
gen_exception(s, s->pc, EXCP_HLT);
}
@ -4528,7 +4518,8 @@ DISAS_INSN(stop)
ext = read_im16(env, s);
gen_set_sr_im(s, ext, 0);
tcg_gen_movi_i32(cpu_halted, 1);
tcg_gen_st_i32(tcg_constant_i32(1), tcg_env,
offsetof(CPUState, halted) - offsetof(M68kCPU, env));
gen_exception(s, s->pc, EXCP_HLT);
}

2
target/microblaze/cpu.h
View file

@ -259,7 +259,7 @@ struct CPUArchState {
/* lwx/swx reserved address */
#define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */
target_ulong res_addr;
uint32_t res_addr;
uint32_t res_val;
/* Internal flags. */

3
target/microblaze/helper.c
View file

@ -274,7 +274,8 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
MemTxAttrs *attrs)
{
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
target_ulong vaddr, paddr = 0;
vaddr vaddr;
hwaddr paddr = 0;
MicroBlazeMMULookup lu;
int mmu_idx = cpu_mmu_index(cs, false);
unsigned int hit;

2
target/microblaze/helper.h
View file

@ -20,7 +20,7 @@ DEF_HELPER_FLAGS_3(fcmp_ne, TCG_CALL_NO_WG, i32, env, i32, i32)
DEF_HELPER_FLAGS_3(fcmp_ge, TCG_CALL_NO_WG, i32, env, i32, i32)
DEF_HELPER_FLAGS_2(pcmpbf, TCG_CALL_NO_RWG_SE, i32, i32, i32)
DEF_HELPER_FLAGS_2(stackprot, TCG_CALL_NO_WG, void, env, tl)
DEF_HELPER_FLAGS_2(stackprot, TCG_CALL_NO_WG, void, env, i32)
DEF_HELPER_FLAGS_2(get, TCG_CALL_NO_RWG, i32, i32, i32)
DEF_HELPER_FLAGS_3(put, TCG_CALL_NO_RWG, void, i32, i32, i32)

6
target/microblaze/machine.c
View file

@ -78,7 +78,7 @@ static const VMStateField vmstate_env_fields[] = {
VMSTATE_UINT32(iflags, CPUMBState),
VMSTATE_UINT32(res_val, CPUMBState),
VMSTATE_UINTTL(res_addr, CPUMBState),
VMSTATE_UINT32(res_addr, CPUMBState),
VMSTATE_STRUCT(mmu, CPUMBState, 0, vmstate_mmu, MicroBlazeMMU),
@ -87,8 +87,8 @@ static const VMStateField vmstate_env_fields[] = {
static const VMStateDescription vmstate_env = {
.name = "env",
.version_id = 0,
.minimum_version_id = 0,
.version_id = 1,
.minimum_version_id = 1,
.fields = vmstate_env_fields,
};

4
target/microblaze/mmu.c
View file

@ -78,7 +78,7 @@ static void mmu_change_pid(CPUMBState *env, unsigned int newpid)
/* rw - 0 = read, 1 = write, 2 = fetch. */
unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
target_ulong vaddr, MMUAccessType rw, int mmu_idx)
vaddr vaddr, MMUAccessType rw, int mmu_idx)
{
MicroBlazeMMU *mmu = &cpu->env.mmu;
unsigned int i, hit = 0;
@ -172,7 +172,7 @@ unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
}
done:
qemu_log_mask(CPU_LOG_MMU,
"MMU vaddr=0x" TARGET_FMT_lx
"MMU vaddr=0x%" VADDR_PRIx
" rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n",
vaddr, rw, tlb_wr, tlb_ex, hit);
return hit;

2
target/microblaze/mmu.h
View file

@ -86,7 +86,7 @@ typedef struct {
} MicroBlazeMMULookup;
unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
target_ulong vaddr, MMUAccessType rw, int mmu_idx);
vaddr vaddr, MMUAccessType rw, int mmu_idx);
uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn);
void mmu_write(CPUMBState *env, bool ea, uint32_t rn, uint32_t v);
void mmu_init(MicroBlazeMMU *mmu);

4
target/microblaze/op_helper.c
View file

@ -365,13 +365,13 @@ uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
return 0;
}
void helper_stackprot(CPUMBState *env, target_ulong addr)
void helper_stackprot(CPUMBState *env, uint32_t addr)
{
if (addr < env->slr || addr > env->shr) {
CPUState *cs = env_cpu(env);
qemu_log_mask(CPU_LOG_INT, "Stack protector violation at "
TARGET_FMT_lx " %x %x\n",
"0x%x 0x%x 0x%x\n",
addr, env->slr, env->shr);
env->ear = addr;

83
target/microblaze/translate.c
View file

@ -55,7 +55,7 @@ static TCGv_i32 cpu_imm;
static TCGv_i32 cpu_bvalue;
static TCGv_i32 cpu_btarget;
static TCGv_i32 cpu_iflags;
static TCGv cpu_res_addr;
static TCGv_i32 cpu_res_addr;
static TCGv_i32 cpu_res_val;
/* This is the state at translation time. */
@ -116,12 +116,12 @@ static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec)
gen_raise_exception_sync(dc, EXCP_HW_EXCP);
}
static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
static void gen_goto_tb(DisasContext *dc, unsigned tb_slot_idx, vaddr dest)
{
if (translator_use_goto_tb(&dc->base, dest)) {
tcg_gen_goto_tb(n);
tcg_gen_goto_tb(tb_slot_idx);
tcg_gen_movi_i32(cpu_pc, dest);
tcg_gen_exit_tb(dc->base.tb, n);
tcg_gen_exit_tb(dc->base.tb, tb_slot_idx);
} else {
tcg_gen_movi_i32(cpu_pc, dest);
tcg_gen_lookup_and_goto_ptr();
@ -604,9 +604,9 @@ static bool trans_wdic(DisasContext *dc, arg_wdic *a)
DO_TYPEA(xor, false, tcg_gen_xor_i32)
DO_TYPEBI(xori, false, tcg_gen_xori_i32)
static TCGv compute_ldst_addr_typea(DisasContext *dc, int ra, int rb)
static TCGv_i32 compute_ldst_addr_typea(DisasContext *dc, int ra, int rb)
{
TCGv ret;
TCGv_i32 ret;
/* If any of the regs is r0, set t to the value of the other reg. */
if (ra && rb) {
@ -626,9 +626,9 @@ static TCGv compute_ldst_addr_typea(DisasContext *dc, int ra, int rb)
return ret;
}
static TCGv compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm)
static TCGv_i32 compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm)
{
TCGv ret;
TCGv_i32 ret;
/* If any of the regs is r0, set t to the value of the other reg. */
if (ra && imm) {
@ -708,7 +708,7 @@ static inline MemOp mo_endian(DisasContext *dc)
return dc->cfg->endi ? MO_LE : MO_BE;
}
static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop,
static bool do_load(DisasContext *dc, int rd, TCGv_i32 addr, MemOp mop,
int mem_index, bool rev)
{
MemOp size = mop & MO_SIZE;
@ -726,7 +726,7 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop,
mop ^= MO_BSWAP;
}
if (size < MO_32) {
tcg_gen_xori_tl(addr, addr, 3 - size);
tcg_gen_xori_i32(addr, addr, 3 - size);
}
}
@ -750,13 +750,13 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop,
static bool trans_lbu(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
TCGv_i32 addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
return do_load(dc, arg->rd, addr, MO_UB, dc->mem_index, false);
}
static bool trans_lbur(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
TCGv_i32 addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
return do_load(dc, arg->rd, addr, MO_UB, dc->mem_index, true);
}
@ -776,19 +776,19 @@ static bool trans_lbuea(DisasContext *dc, arg_typea *arg)
static bool trans_lbui(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
TCGv_i32 addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
return do_load(dc, arg->rd, addr, MO_UB, dc->mem_index, false);
}
static bool trans_lhu(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
TCGv_i32 addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, false);
}
static bool trans_lhur(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
TCGv_i32 addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, true);
}
@ -810,19 +810,19 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg)
static bool trans_lhui(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
TCGv_i32 addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, false);
}
static bool trans_lw(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
TCGv_i32 addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, false);
}
static bool trans_lwr(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
TCGv_i32 addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, true);
}
@ -844,20 +844,20 @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg)
static bool trans_lwi(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
TCGv_i32 addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, false);
}
static bool trans_lwx(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
TCGv_i32 addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
/* lwx does not throw unaligned access errors, so force alignment */
tcg_gen_andi_tl(addr, addr, ~3);
tcg_gen_andi_i32(addr, addr, ~3);
tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index,
mo_endian(dc) | MO_UL);
tcg_gen_mov_tl(cpu_res_addr, addr);
tcg_gen_mov_i32(cpu_res_addr, addr);
if (arg->rd) {
tcg_gen_mov_i32(cpu_R[arg->rd], cpu_res_val);
@ -868,7 +868,7 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg)
return true;
}
static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop,
static bool do_store(DisasContext *dc, int rd, TCGv_i32 addr, MemOp mop,
int mem_index, bool rev)
{
MemOp size = mop & MO_SIZE;
@ -886,7 +886,7 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop,
mop ^= MO_BSWAP;
}
if (size < MO_32) {
tcg_gen_xori_tl(addr, addr, 3 - size);
tcg_gen_xori_i32(addr, addr, 3 - size);
}
}
@ -910,13 +910,13 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop,
static bool trans_sb(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
TCGv_i32 addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
return do_store(dc, arg->rd, addr, MO_UB, dc->mem_index, false);
}
static bool trans_sbr(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
TCGv_i32 addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
return do_store(dc, arg->rd, addr, MO_UB, dc->mem_index, true);
}
@ -936,19 +936,19 @@ static bool trans_sbea(DisasContext *dc, arg_typea *arg)
static bool trans_sbi(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
TCGv_i32 addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
return do_store(dc, arg->rd, addr, MO_UB, dc->mem_index, false);
}
static bool trans_sh(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
TCGv_i32 addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, false);
}
static bool trans_shr(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
TCGv_i32 addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, true);
}
@ -970,19 +970,19 @@ static bool trans_shea(DisasContext *dc, arg_typea *arg)
static bool trans_shi(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
TCGv_i32 addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, false);
}
static bool trans_sw(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
TCGv_i32 addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, false);
}
static bool trans_swr(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
TCGv_i32 addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, true);
}
@ -1004,19 +1004,19 @@ static bool trans_swea(DisasContext *dc, arg_typea *arg)
static bool trans_swi(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
TCGv_i32 addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, false);
}
static bool trans_swx(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
TCGv_i32 addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
TCGLabel *swx_done = gen_new_label();
TCGLabel *swx_fail = gen_new_label();
TCGv_i32 tval;
/* swx does not throw unaligned access errors, so force alignment */
tcg_gen_andi_tl(addr, addr, ~3);
tcg_gen_andi_i32(addr, addr, ~3);
/*
* Compare the address vs the one we used during lwx.
@ -1024,7 +1024,7 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg)
* branch, but we know we can use the equal version in the global.
* In either case, addr is no longer needed.
*/
tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_fail);
tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_addr, addr, swx_fail);
/*
* Compare the value loaded during lwx with current contents of
@ -1052,7 +1052,7 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg)
* Prevent the saved address from working again without another ldx.
* Akin to the pseudocode setting reservation = 0.
*/
tcg_gen_movi_tl(cpu_res_addr, -1);
tcg_gen_movi_i32(cpu_res_addr, RES_ADDR_NONE);
return true;
}
@ -1173,7 +1173,7 @@ static bool trans_brk(DisasContext *dc, arg_typea_br *arg)
tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next);
}
tcg_gen_ori_i32(cpu_msr, cpu_msr, MSR_BIP);
tcg_gen_movi_tl(cpu_res_addr, -1);
tcg_gen_movi_i32(cpu_res_addr, RES_ADDR_NONE);
dc->base.is_jmp = DISAS_EXIT;
return true;
@ -1194,7 +1194,7 @@ static bool trans_brki(DisasContext *dc, arg_typeb_br *arg)
if (arg->rd) {
tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next);
}
tcg_gen_movi_tl(cpu_res_addr, -1);
tcg_gen_movi_i32(cpu_res_addr, RES_ADDR_NONE);
#ifdef CONFIG_USER_ONLY
switch (imm) {
@ -1885,6 +1885,7 @@ void mb_tcg_init(void)
tcg_global_mem_new_i32(tcg_env, i32s[i].ofs, i32s[i].name);
}
cpu_res_addr =
tcg_global_mem_new(tcg_env, offsetof(CPUMBState, res_addr), "res_addr");
cpu_res_addr = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUMBState, res_addr),
"res_addr");
}

7
target/mips/tcg/translate.c
View file

@ -4362,12 +4362,13 @@ static void gen_trap(DisasContext *ctx, uint32_t opc,
}
}
static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx,
target_ulong dest)
{
if (translator_use_goto_tb(&ctx->base, dest)) {
tcg_gen_goto_tb(n);
tcg_gen_goto_tb(tb_slot_idx);
gen_save_pc(dest);
tcg_gen_exit_tb(ctx->base.tb, n);
tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx);
} else {
gen_save_pc(dest);
tcg_gen_lookup_and_goto_ptr();

31
target/openrisc/cpu.h
View file

@ -220,33 +220,24 @@ typedef struct OpenRISCTLBEntry {
typedef struct CPUOpenRISCTLBContext {
OpenRISCTLBEntry itlb[TLB_SIZE];
OpenRISCTLBEntry dtlb[TLB_SIZE];
int (*cpu_openrisc_map_address_code)(OpenRISCCPU *cpu,
hwaddr *physical,
int *prot,
target_ulong address, int rw);
int (*cpu_openrisc_map_address_data)(OpenRISCCPU *cpu,
hwaddr *physical,
int *prot,
target_ulong address, int rw);
} CPUOpenRISCTLBContext;
#endif
typedef struct CPUArchState {
target_ulong shadow_gpr[16][32]; /* Shadow registers */
uint32_t shadow_gpr[16][32]; /* Shadow registers */
target_ulong pc; /* Program counter */
target_ulong ppc; /* Prev PC */
target_ulong jmp_pc; /* Jump PC */
uint32_t pc; /* Program counter */
uint32_t ppc; /* Prev PC */
uint32_t jmp_pc; /* Jump PC */
uint64_t mac; /* Multiply registers MACHI:MACLO */
target_ulong epcr; /* Exception PC register */
target_ulong eear; /* Exception EA register */
uint32_t epcr; /* Exception PC register */
uint32_t eear; /* Exception EA register */
target_ulong sr_f; /* the SR_F bit, values 0, 1. */
target_ulong sr_cy; /* the SR_CY bit, values 0, 1. */
target_long sr_ov; /* the SR_OV bit (in the sign bit only) */
uint32_t sr_f; /* the SR_F bit, values 0, 1. */
uint32_t sr_cy; /* the SR_CY bit, values 0, 1. */
int32_t sr_ov; /* the SR_OV bit (in the sign bit only) */
uint32_t sr; /* Supervisor register, without SR_{F,CY,OV} */
uint32_t esr; /* Exception supervisor register */
uint32_t evbar; /* Exception vector base address register */
@ -254,8 +245,8 @@ typedef struct CPUArchState {
uint32_t fpcsr; /* Float register */
float_status fp_status;
target_ulong lock_addr;
target_ulong lock_value;
uint32_t lock_addr;
uint32_t lock_value;
uint32_t dflag; /* In delay slot (boolean) */

8
target/openrisc/fpu_helper.c
View file

@ -146,10 +146,10 @@ uint32_t helper_float_madd_s(CPUOpenRISCState *env, uint32_t a,
#define FLOAT_CMP(name, impl) \
target_ulong helper_float_ ## name ## _d(CPUOpenRISCState *env, \
uint32_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \
uint64_t fdt0, uint64_t fdt1) \
{ return float64_ ## impl(fdt0, fdt1, &env->fp_status); } \
target_ulong helper_float_ ## name ## _s(CPUOpenRISCState *env, \
uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \
uint32_t fdt0, uint32_t fdt1) \
{ return float32_ ## impl(fdt0, fdt1, &env->fp_status); }
@ -160,13 +160,13 @@ FLOAT_CMP(un, unordered_quiet)
#undef FLOAT_CMP
#define FLOAT_UCMP(name, expr) \
target_ulong helper_float_ ## name ## _d(CPUOpenRISCState *env, \
uint32_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \
uint64_t fdt0, uint64_t fdt1) \
{ \
FloatRelation r = float64_compare_quiet(fdt0, fdt1, &env->fp_status); \
return expr; \
} \
target_ulong helper_float_ ## name ## _s(CPUOpenRISCState *env, \
uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \
uint32_t fdt0, uint32_t fdt1) \
{ \
FloatRelation r = float32_compare_quiet(fdt0, fdt1, &env->fp_status); \

8
target/openrisc/helper.h
View file

@ -47,8 +47,8 @@ FOP_CALC(rem)
#undef FOP_CALC
#define FOP_CMP(op) \
DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_RWG, tl, env, i32, i32) \
DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_RWG, tl, env, i64, i64)
DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_RWG, i32, env, i32, i32) \
DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_RWG, i32, env, i64, i64)
FOP_CMP(eq)
FOP_CMP(lt)
FOP_CMP(le)
@ -62,5 +62,5 @@ FOP_CMP(ult)
DEF_HELPER_FLAGS_1(rfe, 0, void, env)
/* sys */
DEF_HELPER_FLAGS_3(mtspr, 0, void, env, tl, tl)
DEF_HELPER_FLAGS_3(mfspr, TCG_CALL_NO_WG, tl, env, tl, tl)
DEF_HELPER_FLAGS_3(mtspr, 0, void, env, i32, i32)
DEF_HELPER_FLAGS_3(mfspr, TCG_CALL_NO_WG, i32, env, i32, i32)

20
target/openrisc/machine.c
View file

@ -26,8 +26,8 @@ static const VMStateDescription vmstate_tlb_entry = {
.version_id = 1,
.minimum_version_id = 1,
.fields = (const VMStateField[]) {
VMSTATE_UINTTL(mr, OpenRISCTLBEntry),
VMSTATE_UINTTL(tr, OpenRISCTLBEntry),
VMSTATE_UINT32(mr, OpenRISCTLBEntry),
VMSTATE_UINT32(tr, OpenRISCTLBEntry),
VMSTATE_END_OF_LIST()
}
};
@ -72,14 +72,14 @@ static const VMStateDescription vmstate_env = {
.version_id = 6,
.minimum_version_id = 6,
.fields = (const VMStateField[]) {
VMSTATE_UINTTL_2DARRAY(shadow_gpr, CPUOpenRISCState, 16, 32),
VMSTATE_UINTTL(pc, CPUOpenRISCState),
VMSTATE_UINTTL(ppc, CPUOpenRISCState),
VMSTATE_UINTTL(jmp_pc, CPUOpenRISCState),
VMSTATE_UINTTL(lock_addr, CPUOpenRISCState),
VMSTATE_UINTTL(lock_value, CPUOpenRISCState),
VMSTATE_UINTTL(epcr, CPUOpenRISCState),
VMSTATE_UINTTL(eear, CPUOpenRISCState),
VMSTATE_UINT32_2DARRAY(shadow_gpr, CPUOpenRISCState, 16, 32),
VMSTATE_UINT32(pc, CPUOpenRISCState),
VMSTATE_UINT32(ppc, CPUOpenRISCState),
VMSTATE_UINT32(jmp_pc, CPUOpenRISCState),
VMSTATE_UINT32(lock_addr, CPUOpenRISCState),
VMSTATE_UINT32(lock_value, CPUOpenRISCState),
VMSTATE_UINT32(epcr, CPUOpenRISCState),
VMSTATE_UINT32(eear, CPUOpenRISCState),
/* Save the architecture value of the SR, not the internally
expanded version. Since this architecture value does not

7
target/openrisc/mmu.c
View file

@ -28,15 +28,14 @@
#include "qemu/host-utils.h"
#include "hw/loader.h"
static inline void get_phys_nommu(hwaddr *phys_addr, int *prot,
target_ulong address)
static void get_phys_nommu(hwaddr *phys_addr, int *prot, vaddr address)
{
*phys_addr = address;
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
}
static int get_phys_mmu(OpenRISCCPU *cpu, hwaddr *phys_addr, int *prot,
target_ulong addr, int need, bool super)
vaddr addr, int need, bool super)
{
int idx = (addr >> TARGET_PAGE_BITS) & TLB_MASK;
uint32_t imr = cpu->env.tlb.itlb[idx].mr;
@ -95,7 +94,7 @@ static int get_phys_mmu(OpenRISCCPU *cpu, hwaddr *phys_addr, int *prot,
}
}
static void raise_mmu_exception(OpenRISCCPU *cpu, target_ulong address,
static void raise_mmu_exception(OpenRISCCPU *cpu, vaddr address,
int exception)
{
CPUState *cs = CPU(cpu);

7
target/openrisc/sys_helper.c
View file

@ -40,12 +40,12 @@ static inline bool is_user(CPUOpenRISCState *env)
#endif
}
void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
void HELPER(mtspr)(CPUOpenRISCState *env, uint32_t spr, uint32_t rb)
{
OpenRISCCPU *cpu = env_archcpu(env);
#ifndef CONFIG_USER_ONLY
CPUState *cs = env_cpu(env);
target_ulong mr;
uint32_t mr;
int idx;
#endif
@ -213,8 +213,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
#endif
}
target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
target_ulong spr)
uint32_t HELPER(mfspr)(CPUOpenRISCState *env, uint32_t rd, uint32_t spr)
{
OpenRISCCPU *cpu = env_archcpu(env);
#ifndef CONFIG_USER_ONLY

463
target/openrisc/translate.c
View file

File diff suppressed because it is too large Load diff

7
target/ppc/translate.c
View file

@ -3668,16 +3668,17 @@ static void gen_lookup_and_goto_ptr(DisasContext *ctx)
}
/*** Branch ***/
static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx,
target_ulong dest)
{
if (NARROW_MODE(ctx)) {
dest = (uint32_t) dest;
}
if (use_goto_tb(ctx, dest)) {
pmu_count_insns(ctx);
tcg_gen_goto_tb(n);
tcg_gen_goto_tb(tb_slot_idx);
tcg_gen_movi_tl(cpu_nip, dest & ~3);
tcg_gen_exit_tb(ctx->base.tb, n);
tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx);
} else {
tcg_gen_movi_tl(cpu_nip, dest & ~3);
gen_lookup_and_goto_ptr(ctx);

4
target/riscv/cpu.h
View file

@ -50,7 +50,7 @@ typedef struct CPUArchState CPURISCVState;
*/
#define RISCV_UW2_ALWAYS_STORE_AMO 1
#define RV(x) ((target_ulong)1 << (x - 'A'))
#define RV(x) BIT(x - 'A')
/*
* Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[]
@ -582,7 +582,7 @@ struct RISCVCPUClass {
RISCVCPUDef *def;
};
static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
static inline int riscv_has_ext(CPURISCVState *env, uint32_t ext)
{
return (env->misa_ext & ext) != 0;
}

16
target/riscv/insn_trans/trans_rvv.c.inc
View file

@ -3351,19 +3351,19 @@ static void load_element(TCGv_i64 dest, TCGv_ptr base,
/* offset of the idx element with base register r */
static uint32_t endian_ofs(DisasContext *s, int r, int idx)
{
#if HOST_BIG_ENDIAN
return vreg_ofs(s, r) + ((idx ^ (7 >> s->sew)) << s->sew);
#else
return vreg_ofs(s, r) + (idx << s->sew);
#endif
if (HOST_BIG_ENDIAN) {
return vreg_ofs(s, r) + ((idx ^ (7 >> s->sew)) << s->sew);
} else {
return vreg_ofs(s, r) + (idx << s->sew);
}
}
/* adjust the index according to the endian */
static void endian_adjust(TCGv_i32 ofs, int sew)
{
#if HOST_BIG_ENDIAN
tcg_gen_xori_i32(ofs, ofs, 7 >> sew);
#endif
if (HOST_BIG_ENDIAN) {
tcg_gen_xori_i32(ofs, ofs, 7 >> sew);
}
}
/* Load idx >= VLMAX ? 0 : vreg[idx] */

6
target/riscv/kvm/kvm-cpu.c
View file

@ -36,6 +36,7 @@
#include "hw/pci/pci.h"
#include "exec/memattrs.h"
#include "system/address-spaces.h"
#include "system/memory.h"
#include "hw/boards.h"
#include "hw/irq.h"
#include "hw/intc/riscv_imsic.h"
@ -1564,6 +1565,7 @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
{
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
g_autofree uint8_t *buf = NULL;
RISCVCPU *cpu = RISCV_CPU(cs);
target_ulong num_bytes;
@ -1602,9 +1604,9 @@ static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
exit(1);
}
cpu_physical_memory_write(addr, buf, ret);
address_space_write(cs->as, addr, attrs, buf, ret);
} else {
cpu_physical_memory_read(addr, buf, num_bytes);
address_space_read(cs->as, addr, attrs, buf, num_bytes);
ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
if (ret < 0) {

12
target/riscv/monitor.c
View file

@ -23,6 +23,7 @@
#include "cpu_bits.h"
#include "monitor/monitor.h"
#include "monitor/hmp-target.h"
#include "system/memory.h"
#ifdef TARGET_RISCV64
#define PTE_HEADER_FIELDS "vaddr paddr "\
@ -77,11 +78,13 @@ static void print_pte(Monitor *mon, int va_bits, target_ulong vaddr,
attr & PTE_D ? 'd' : '-');
}
static void walk_pte(Monitor *mon, hwaddr base, target_ulong start,
static void walk_pte(Monitor *mon, AddressSpace *as,
hwaddr base, target_ulong start,
int level, int ptidxbits, int ptesize, int va_bits,
target_ulong *vbase, hwaddr *pbase, hwaddr *last_paddr,
target_ulong *last_size, int *last_attr)
{
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
hwaddr pte_addr;
hwaddr paddr;
target_ulong last_start = -1;
@ -100,7 +103,7 @@ static void walk_pte(Monitor *mon, hwaddr base, target_ulong start,
for (idx = 0; idx < (1UL << ptidxbits); idx++) {
pte_addr = base + idx * ptesize;
cpu_physical_memory_read(pte_addr, &pte, ptesize);
address_space_read(as, pte_addr, attrs, &pte, ptesize);
paddr = (hwaddr)(pte >> PTE_PPN_SHIFT) << PGSHIFT;
attr = pte & 0xff;
@ -132,7 +135,7 @@ static void walk_pte(Monitor *mon, hwaddr base, target_ulong start,
*last_size = pgsize;
} else {
/* pointer to the next level of the page table */
walk_pte(mon, paddr, start, level - 1, ptidxbits, ptesize,
walk_pte(mon, as, paddr, start, level - 1, ptidxbits, ptesize,
va_bits, vbase, pbase, last_paddr,
last_size, last_attr);
}
@ -145,6 +148,7 @@ static void walk_pte(Monitor *mon, hwaddr base, target_ulong start,
static void mem_info_svxx(Monitor *mon, CPUArchState *env)
{
AddressSpace *as = env_cpu(env)->as;
int levels, ptidxbits, ptesize, vm, va_bits;
hwaddr base;
target_ulong vbase;
@ -199,7 +203,7 @@ static void mem_info_svxx(Monitor *mon, CPUArchState *env)
last_attr = 0;
/* walk page tables, starting from address 0 */
walk_pte(mon, base, 0, levels - 1, ptidxbits, ptesize, va_bits,
walk_pte(mon, as, base, 0, levels - 1, ptidxbits, ptesize, va_bits,
&vbase, &pbase, &last_paddr, &last_size, &last_attr);
/* don't forget the last one */

9
target/riscv/translate.c
View file

@ -286,7 +286,8 @@ static void exit_tb(DisasContext *ctx)
tcg_gen_exit_tb(NULL, 0);
}
static void gen_goto_tb(DisasContext *ctx, int n, target_long diff)
static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx,
target_long diff)
{
target_ulong dest = ctx->base.pc_next + diff;
@ -305,12 +306,12 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_long diff)
*/
if (tb_cflags(ctx->base.tb) & CF_PCREL) {
gen_update_pc(ctx, diff);
tcg_gen_goto_tb(n);
tcg_gen_goto_tb(tb_slot_idx);
} else {
tcg_gen_goto_tb(n);
tcg_gen_goto_tb(tb_slot_idx);
gen_update_pc(ctx, diff);
}
tcg_gen_exit_tb(ctx->base.tb, n);
tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx);
} else {
gen_update_pc(ctx, diff);
lookup_and_goto_ptr(ctx);

32
target/riscv/vector_helper.c
View file

@ -235,26 +235,26 @@ vext_continuous_ldst_host(CPURISCVState *env, vext_ldst_elem_fn_host *ldst_host,
void *vd, uint32_t evl, uint32_t reg_start, void *host,
uint32_t esz, bool is_load)
{
#if HOST_BIG_ENDIAN
for (; reg_start < evl; reg_start++, host += esz) {
ldst_host(vd, reg_start, host);
}
#else
if (esz == 1) {
uint32_t byte_offset = reg_start * esz;
uint32_t size = (evl - reg_start) * esz;
if (is_load) {
memcpy(vd + byte_offset, host, size);
} else {
memcpy(host, vd + byte_offset, size);
}
} else {
if (HOST_BIG_ENDIAN) {
for (; reg_start < evl; reg_start++, host += esz) {
ldst_host(vd, reg_start, host);
}
} else {
if (esz == 1) {
uint32_t byte_offset = reg_start * esz;
uint32_t size = (evl - reg_start) * esz;
if (is_load) {
memcpy(vd + byte_offset, host, size);
} else {
memcpy(host, vd + byte_offset, size);
}
} else {
for (; reg_start < evl; reg_start++, host += esz) {
ldst_host(vd, reg_start, host);
}
}
}
#endif
}
static void vext_set_tail_elems_1s(target_ulong vl, void *vd,

462
target/rx/translate.c
View file

File diff suppressed because it is too large Load diff

6
target/s390x/tcg/translate.c
View file

@ -258,9 +258,9 @@ static inline int vec_reg_offset(uint8_t reg, uint8_t enr, MemOp es)
* 16 byte operations to handle it in a special way.
*/
g_assert(es <= MO_64);
#if !HOST_BIG_ENDIAN
offs ^= (8 - bytes);
#endif
if (!HOST_BIG_ENDIAN) {
offs ^= (8 - bytes);
}
return offs + vec_full_reg_offset(reg);
}

6
target/s390x/tcg/translate_vx.c.inc
View file

@ -175,9 +175,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
/* convert it to an element offset relative to tcg_env (vec_reg_offset() */
tcg_gen_shli_i64(tmp, tmp, es);
#if !HOST_BIG_ENDIAN
tcg_gen_xori_i64(tmp, tmp, 8 - NUM_VEC_ELEMENT_BYTES(es));
#endif
if (!HOST_BIG_ENDIAN) {
tcg_gen_xori_i64(tmp, tmp, 8 - NUM_VEC_ELEMENT_BYTES(es));
}
tcg_gen_addi_i64(tmp, tmp, vec_full_reg_offset(reg));
/* generate the final ptr by adding tcg_env */

6
target/sh4/cpu.h
View file

@ -277,7 +277,7 @@ void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
uint32_t mem_value);
#endif
int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
int cpu_sh4_is_cached(CPUSH4State *env, uint32_t addr);
void cpu_load_tlb(CPUSH4State * env);
@ -365,14 +365,14 @@ static inline int cpu_ptel_pr (uint32_t ptel)
#define PTEA_TC (1 << 3)
#define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)
static inline target_ulong cpu_read_sr(CPUSH4State *env)
static inline uint32_t cpu_read_sr(CPUSH4State *env)
{
return env->sr | (env->sr_m << SR_M) |
(env->sr_q << SR_Q) |
(env->sr_t << SR_T);
}
static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr)
static inline void cpu_write_sr(CPUSH4State *env, uint32_t sr)
{
env->sr_m = (sr >> SR_M) & 1;
env->sr_q = (sr >> SR_Q) & 1;

34
target/sh4/helper.c
View file

@ -47,7 +47,7 @@
#if defined(CONFIG_USER_ONLY)
int cpu_sh4_is_cached(CPUSH4State *env, target_ulong addr)
int cpu_sh4_is_cached(CPUSH4State *env, uint32_t addr)
{
/* For user mode, only U0 area is cacheable. */
return !(addr & 0x80000000);
@ -231,11 +231,11 @@ static int itlb_replacement(CPUSH4State * env)
/* Find the corresponding entry in the right TLB
Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
*/
static int find_tlb_entry(CPUSH4State * env, target_ulong address,
static int find_tlb_entry(CPUSH4State *env, vaddr address,
tlb_t * entries, uint8_t nbtlb, int use_asid)
{
int match = MMU_DTLB_MISS;
uint32_t start, end;
vaddr start, end;
uint8_t asid;
int i;
@ -291,7 +291,7 @@ static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
/* Find itlb entry
Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
*/
static int find_itlb_entry(CPUSH4State * env, target_ulong address,
static int find_itlb_entry(CPUSH4State *env, vaddr address,
int use_asid)
{
int e;
@ -309,7 +309,7 @@ static int find_itlb_entry(CPUSH4State * env, target_ulong address,
/* Find utlb entry
Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid)
static int find_utlb_entry(CPUSH4State *env, vaddr address, int use_asid)
{
/* per utlb access */
increment_urc(env);
@ -325,8 +325,8 @@ static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid
MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
*/
static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
int *prot, target_ulong address,
static int get_mmu_address(CPUSH4State *env, hwaddr *physical,
int *prot, vaddr address,
MMUAccessType access_type)
{
int use_asid, n;
@ -392,8 +392,8 @@ static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
return n;
}
static int get_physical_address(CPUSH4State * env, target_ulong * physical,
int *prot, target_ulong address,
static int get_physical_address(CPUSH4State *env, hwaddr* physical,
int *prot, vaddr address,
MMUAccessType access_type)
{
/* P1, P2 and P4 areas do not use translation */
@ -433,7 +433,7 @@ static int get_physical_address(CPUSH4State * env, target_ulong * physical,
hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
target_ulong physical;
hwaddr physical;
int prot;
if (get_physical_address(cpu_env(cs), &physical, &prot, addr, MMU_DATA_LOAD)
@ -452,7 +452,7 @@ void cpu_load_tlb(CPUSH4State * env)
if (entry->v) {
/* Overwriting valid entry in utlb. */
target_ulong address = entry->vpn << 10;
vaddr address = entry->vpn << 10;
tlb_flush_page(cs, address);
}
@ -528,7 +528,7 @@ void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
tlb_t * entry = &s->itlb[index];
if (entry->v) {
/* Overwriting valid entry in itlb. */
target_ulong address = entry->vpn << 10;
vaddr address = entry->vpn << 10;
tlb_flush_page(env_cpu(s), address);
}
entry->asid = asid;
@ -570,7 +570,7 @@ void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
/* ITLB Data Array 1 */
if (entry->v) {
/* Overwriting valid entry in utlb. */
target_ulong address = entry->vpn << 10;
vaddr address = entry->vpn << 10;
tlb_flush_page(env_cpu(s), address);
}
entry->ppn = (mem_value & 0x1ffffc00) >> 10;
@ -665,7 +665,7 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
CPUState *cs = env_cpu(s);
/* Overwriting valid entry in utlb. */
target_ulong address = entry->vpn << 10;
vaddr address = entry->vpn << 10;
tlb_flush_page(cs, address);
}
entry->asid = asid;
@ -716,7 +716,7 @@ void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
/* UTLB Data Array 1 */
if (entry->v) {
/* Overwriting valid entry in utlb. */
target_ulong address = entry->vpn << 10;
vaddr address = entry->vpn << 10;
tlb_flush_page(env_cpu(s), address);
}
entry->ppn = (mem_value & 0x1ffffc00) >> 10;
@ -735,7 +735,7 @@ void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
}
}
int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
int cpu_sh4_is_cached(CPUSH4State *env, uint32_t addr)
{
int n;
int use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD));
@ -800,7 +800,7 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
CPUSH4State *env = cpu_env(cs);
int ret;
target_ulong physical;
hwaddr physical;
int prot;
ret = get_physical_address(env, &physical, &prot, address, access_type);

10
target/sh4/translate.c
View file

@ -223,7 +223,7 @@ static inline bool use_exit_tb(DisasContext *ctx)
return (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) != 0;
}
static bool use_goto_tb(DisasContext *ctx, target_ulong dest)
static bool use_goto_tb(DisasContext *ctx, vaddr dest)
{
if (use_exit_tb(ctx)) {
return false;
@ -231,12 +231,12 @@ static bool use_goto_tb(DisasContext *ctx, target_ulong dest)
return translator_use_goto_tb(&ctx->base, dest);
}
static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx, vaddr dest)
{
if (use_goto_tb(ctx, dest)) {
tcg_gen_goto_tb(n);
tcg_gen_goto_tb(tb_slot_idx);
tcg_gen_movi_i32(cpu_pc, dest);
tcg_gen_exit_tb(ctx->base.tb, n);
tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx);
} else {
tcg_gen_movi_i32(cpu_pc, dest);
if (use_exit_tb(ctx)) {
@ -267,7 +267,7 @@ static void gen_jump(DisasContext * ctx)
}
/* Immediate conditional jump (bt or bf) */
static void gen_conditional_jump(DisasContext *ctx, target_ulong dest,
static void gen_conditional_jump(DisasContext *ctx, vaddr dest,
bool jump_if_true)
{
TCGLabel *l1 = gen_new_label();

1
target/sparc/cpu.h
View file

@ -3,7 +3,6 @@
#include "qemu/bswap.h"
#include "cpu-qom.h"
#include "exec/cpu-common.h"
#include "exec/cpu-defs.h"
#include "exec/cpu-interrupt.h"
#include "qemu/cpu-float.h"

1
target/sparc/helper.c
View file

@ -21,6 +21,7 @@
#include "cpu.h"
#include "qemu/timer.h"
#include "qemu/host-utils.h"
#include "exec/cpu-common.h"
#include "exec/helper-proto.h"
void cpu_raise_exception_ra(CPUSPARCState *env, int tt, uintptr_t ra)

1
target/sparc/int64_helper.c
View file

@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "qemu/main-loop.h"
#include "cpu.h"
#include "exec/cpu-common.h"
#include "exec/helper-proto.h"
#include "exec/log.h"
#include "trace.h"

6
target/sparc/translate.c
View file

@ -363,15 +363,15 @@ static bool use_goto_tb(DisasContext *s, target_ulong pc, target_ulong npc)
translator_use_goto_tb(&s->base, npc);
}
static void gen_goto_tb(DisasContext *s, int tb_num,
static void gen_goto_tb(DisasContext *s, unsigned tb_slot_idx,
target_ulong pc, target_ulong npc)
{
if (use_goto_tb(s, pc, npc)) {
/* jump to same page: we can use a direct jump */
tcg_gen_goto_tb(tb_num);
tcg_gen_goto_tb(tb_slot_idx);
tcg_gen_movi_tl(cpu_pc, pc);
tcg_gen_movi_tl(cpu_npc, npc);
tcg_gen_exit_tb(s->base.tb, tb_num);
tcg_gen_exit_tb(s->base.tb, tb_slot_idx);
} else {
/* jump to another page: we can use an indirect jump */
tcg_gen_movi_tl(cpu_pc, pc);

2
target/tricore/cpu.c
View file

@ -37,7 +37,7 @@ static const gchar *tricore_gdb_arch_name(CPUState *cs)
static void tricore_cpu_set_pc(CPUState *cs, vaddr value)
{
cpu_env(cs)->PC = value & ~(target_ulong)1;
cpu_env(cs)->PC = value & ~1;
}
static vaddr tricore_cpu_get_pc(CPUState *cs)

4
target/tricore/helper.c
View file

@ -35,7 +35,7 @@ enum {
};
static int get_physical_address(CPUTriCoreState *env, hwaddr *physical,
int *prot, target_ulong address,
int *prot, vaddr address,
MMUAccessType access_type, int mmu_idx)
{
int ret = TLBRET_MATCH;
@ -61,7 +61,7 @@ hwaddr tricore_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
}
/* TODO: Add exception support */
static void raise_mmu_exception(CPUTriCoreState *env, target_ulong address,
static void raise_mmu_exception(CPUTriCoreState *env, vaddr address,
int rw, int tlb_error)
{
}

219
target/tricore/op_helper.c
View file

@ -149,15 +149,15 @@ static uint32_t ssov32(CPUTriCoreState *env, int64_t arg)
if (arg > max_pos) {
env->PSW_USB_V = (1 << 31);
env->PSW_USB_SV = (1 << 31);
ret = (target_ulong)max_pos;
ret = (uint32_t)max_pos;
} else {
if (arg < max_neg) {
env->PSW_USB_V = (1 << 31);
env->PSW_USB_SV = (1 << 31);
ret = (target_ulong)max_neg;
ret = (uint32_t)max_neg;
} else {
env->PSW_USB_V = 0;
ret = (target_ulong)arg;
ret = (uint32_t)arg;
}
}
env->PSW_USB_AV = arg ^ arg * 2u;
@ -172,10 +172,10 @@ static uint32_t suov32_pos(CPUTriCoreState *env, uint64_t arg)
if (arg > max_pos) {
env->PSW_USB_V = (1 << 31);
env->PSW_USB_SV = (1 << 31);
ret = (target_ulong)max_pos;
ret = (uint32_t)max_pos;
} else {
env->PSW_USB_V = 0;
ret = (target_ulong)arg;
ret = (uint32_t)arg;
}
env->PSW_USB_AV = arg ^ arg * 2u;
env->PSW_USB_SAV |= env->PSW_USB_AV;
@ -192,7 +192,7 @@ static uint32_t suov32_neg(CPUTriCoreState *env, int64_t arg)
ret = 0;
} else {
env->PSW_USB_V = 0;
ret = (target_ulong)arg;
ret = (uint32_t)arg;
}
env->PSW_USB_AV = arg ^ arg * 2u;
env->PSW_USB_SAV |= env->PSW_USB_AV;
@ -260,8 +260,7 @@ static uint32_t suov16(CPUTriCoreState *env, int32_t hw0, int32_t hw1)
return (hw0 & 0xffff) | (hw1 << 16);
}
target_ulong helper_add_ssov(CPUTriCoreState *env, target_ulong r1,
target_ulong r2)
uint32_t helper_add_ssov(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int64_t t1 = sextract64(r1, 0, 32);
int64_t t2 = sextract64(r2, 0, 32);
@ -294,8 +293,7 @@ uint64_t helper_add64_ssov(CPUTriCoreState *env, uint64_t r1, uint64_t r2)
return result;
}
target_ulong helper_add_h_ssov(CPUTriCoreState *env, target_ulong r1,
target_ulong r2)
uint32_t helper_add_h_ssov(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int32_t ret_hw0, ret_hw1;
@ -397,8 +395,7 @@ uint32_t helper_addsur_h_ssov(CPUTriCoreState *env, uint64_t r1, uint32_t r2_l,
}
target_ulong helper_add_suov(CPUTriCoreState *env, target_ulong r1,
target_ulong r2)
uint32_t helper_add_suov(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int64_t t1 = extract64(r1, 0, 32);
int64_t t2 = extract64(r2, 0, 32);
@ -406,8 +403,7 @@ target_ulong helper_add_suov(CPUTriCoreState *env, target_ulong r1,
return suov32_pos(env, result);
}
target_ulong helper_add_h_suov(CPUTriCoreState *env, target_ulong r1,
target_ulong r2)
uint32_t helper_add_h_suov(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int32_t ret_hw0, ret_hw1;
@ -416,8 +412,7 @@ target_ulong helper_add_h_suov(CPUTriCoreState *env, target_ulong r1,
return suov16(env, ret_hw0, ret_hw1);
}
target_ulong helper_sub_ssov(CPUTriCoreState *env, target_ulong r1,
target_ulong r2)
uint32_t helper_sub_ssov(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int64_t t1 = sextract64(r1, 0, 32);
int64_t t2 = sextract64(r2, 0, 32);
@ -450,8 +445,7 @@ uint64_t helper_sub64_ssov(CPUTriCoreState *env, uint64_t r1, uint64_t r2)
return result;
}
target_ulong helper_sub_h_ssov(CPUTriCoreState *env, target_ulong r1,
target_ulong r2)
uint32_t helper_sub_h_ssov(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int32_t ret_hw0, ret_hw1;
@ -552,8 +546,7 @@ uint32_t helper_subadr_h_ssov(CPUTriCoreState *env, uint64_t r1, uint32_t r2_l,
return (result1 & 0xffff0000ULL) | ((result0 >> 16) & 0xffffULL);
}
target_ulong helper_sub_suov(CPUTriCoreState *env, target_ulong r1,
target_ulong r2)
uint32_t helper_sub_suov(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int64_t t1 = extract64(r1, 0, 32);
int64_t t2 = extract64(r2, 0, 32);
@ -561,8 +554,7 @@ target_ulong helper_sub_suov(CPUTriCoreState *env, target_ulong r1,
return suov32_neg(env, result);
}
target_ulong helper_sub_h_suov(CPUTriCoreState *env, target_ulong r1,
target_ulong r2)
uint32_t helper_sub_h_suov(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int32_t ret_hw0, ret_hw1;
@ -571,8 +563,7 @@ target_ulong helper_sub_h_suov(CPUTriCoreState *env, target_ulong r1,
return suov16(env, ret_hw0, ret_hw1);
}
target_ulong helper_mul_ssov(CPUTriCoreState *env, target_ulong r1,
target_ulong r2)
uint32_t helper_mul_ssov(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int64_t t1 = sextract64(r1, 0, 32);
int64_t t2 = sextract64(r2, 0, 32);
@ -580,8 +571,7 @@ target_ulong helper_mul_ssov(CPUTriCoreState *env, target_ulong r1,
return ssov32(env, result);
}
target_ulong helper_mul_suov(CPUTriCoreState *env, target_ulong r1,
target_ulong r2)
uint32_t helper_mul_suov(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int64_t t1 = extract64(r1, 0, 32);
int64_t t2 = extract64(r2, 0, 32);
@ -590,8 +580,7 @@ target_ulong helper_mul_suov(CPUTriCoreState *env, target_ulong r1,
return suov32_pos(env, result);
}
target_ulong helper_sha_ssov(CPUTriCoreState *env, target_ulong r1,
target_ulong r2)
uint32_t helper_sha_ssov(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int64_t t1 = sextract64(r1, 0, 32);
int32_t t2 = sextract64(r2, 0, 6);
@ -606,14 +595,14 @@ target_ulong helper_sha_ssov(CPUTriCoreState *env, target_ulong r1,
return ssov32(env, result);
}
uint32_t helper_abs_ssov(CPUTriCoreState *env, target_ulong r1)
uint32_t helper_abs_ssov(CPUTriCoreState *env, uint32_t r1)
{
target_ulong result;
uint32_t result;
result = ((int32_t)r1 >= 0) ? r1 : (0 - r1);
return ssov32(env, result);
}
uint32_t helper_abs_h_ssov(CPUTriCoreState *env, target_ulong r1)
uint32_t helper_abs_h_ssov(CPUTriCoreState *env, uint32_t r1)
{
int32_t ret_h0, ret_h1;
@ -626,8 +615,7 @@ uint32_t helper_abs_h_ssov(CPUTriCoreState *env, target_ulong r1)
return ssov16(env, ret_h0, ret_h1);
}
target_ulong helper_absdif_ssov(CPUTriCoreState *env, target_ulong r1,
target_ulong r2)
uint32_t helper_absdif_ssov(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int64_t t1 = sextract64(r1, 0, 32);
int64_t t2 = sextract64(r2, 0, 32);
@ -641,8 +629,7 @@ target_ulong helper_absdif_ssov(CPUTriCoreState *env, target_ulong r1,
return ssov32(env, result);
}
uint32_t helper_absdif_h_ssov(CPUTriCoreState *env, target_ulong r1,
target_ulong r2)
uint32_t helper_absdif_h_ssov(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int32_t t1, t2;
int32_t ret_h0, ret_h1;
@ -666,8 +653,8 @@ uint32_t helper_absdif_h_ssov(CPUTriCoreState *env, target_ulong r1,
return ssov16(env, ret_h0, ret_h1);
}
target_ulong helper_madd32_ssov(CPUTriCoreState *env, target_ulong r1,
target_ulong r2, target_ulong r3)
uint32_t helper_madd32_ssov(CPUTriCoreState *env, uint32_t r1,
uint32_t r2, uint32_t r3)
{
int64_t t1 = sextract64(r1, 0, 32);
int64_t t2 = sextract64(r2, 0, 32);
@ -678,8 +665,8 @@ target_ulong helper_madd32_ssov(CPUTriCoreState *env, target_ulong r1,
return ssov32(env, result);
}
target_ulong helper_madd32_suov(CPUTriCoreState *env, target_ulong r1,
target_ulong r2, target_ulong r3)
uint32_t helper_madd32_suov(CPUTriCoreState *env, uint32_t r1,
uint32_t r2, uint32_t r3)
{
uint64_t t1 = extract64(r1, 0, 32);
uint64_t t2 = extract64(r2, 0, 32);
@ -690,8 +677,8 @@ target_ulong helper_madd32_suov(CPUTriCoreState *env, target_ulong r1,
return suov32_pos(env, result);
}
uint64_t helper_madd64_ssov(CPUTriCoreState *env, target_ulong r1,
uint64_t r2, target_ulong r3)
uint64_t helper_madd64_ssov(CPUTriCoreState *env, uint32_t r1,
uint64_t r2, uint32_t r3)
{
uint64_t ret, ovf;
int64_t t1 = sextract64(r1, 0, 32);
@ -848,8 +835,8 @@ uint32_t helper_maddr_q_ssov(CPUTriCoreState *env, uint32_t r1, uint32_t r2,
return ret & 0xffff0000ll;
}
uint64_t helper_madd64_suov(CPUTriCoreState *env, target_ulong r1,
uint64_t r2, target_ulong r3)
uint64_t helper_madd64_suov(CPUTriCoreState *env, uint32_t r1,
uint64_t r2, uint32_t r3)
{
uint64_t ret, mul;
uint64_t t1 = extract64(r1, 0, 32);
@ -873,8 +860,8 @@ uint64_t helper_madd64_suov(CPUTriCoreState *env, target_ulong r1,
return ret;
}
target_ulong helper_msub32_ssov(CPUTriCoreState *env, target_ulong r1,
target_ulong r2, target_ulong r3)
uint32_t helper_msub32_ssov(CPUTriCoreState *env, uint32_t r1,
uint32_t r2, uint32_t r3)
{
int64_t t1 = sextract64(r1, 0, 32);
int64_t t2 = sextract64(r2, 0, 32);
@ -885,8 +872,8 @@ target_ulong helper_msub32_ssov(CPUTriCoreState *env, target_ulong r1,
return ssov32(env, result);
}
target_ulong helper_msub32_suov(CPUTriCoreState *env, target_ulong r1,
target_ulong r2, target_ulong r3)
uint32_t helper_msub32_suov(CPUTriCoreState *env, uint32_t r1,
uint32_t r2, uint32_t r3)
{
uint64_t t1 = extract64(r1, 0, 32);
uint64_t t2 = extract64(r2, 0, 32);
@ -912,8 +899,8 @@ target_ulong helper_msub32_suov(CPUTriCoreState *env, target_ulong r1,
return result;
}
uint64_t helper_msub64_ssov(CPUTriCoreState *env, target_ulong r1,
uint64_t r2, target_ulong r3)
uint64_t helper_msub64_ssov(CPUTriCoreState *env, uint32_t r1,
uint64_t r2, uint32_t r3)
{
uint64_t ret, ovf;
int64_t t1 = sextract64(r1, 0, 32);
@ -944,8 +931,8 @@ uint64_t helper_msub64_ssov(CPUTriCoreState *env, target_ulong r1,
return ret;
}
uint64_t helper_msub64_suov(CPUTriCoreState *env, target_ulong r1,
uint64_t r2, target_ulong r3)
uint64_t helper_msub64_suov(CPUTriCoreState *env, uint32_t r1,
uint64_t r2, uint32_t r3)
{
uint64_t ret, mul;
uint64_t t1 = extract64(r1, 0, 32);
@ -1097,7 +1084,7 @@ uint32_t helper_msubr_q_ssov(CPUTriCoreState *env, uint32_t r1, uint32_t r2,
return ret & 0xffff0000ll;
}
uint32_t helper_abs_b(CPUTriCoreState *env, target_ulong arg)
uint32_t helper_abs_b(CPUTriCoreState *env, uint32_t arg)
{
int32_t b, i;
int32_t ovf = 0;
@ -1120,7 +1107,7 @@ uint32_t helper_abs_b(CPUTriCoreState *env, target_ulong arg)
return ret;
}
uint32_t helper_abs_h(CPUTriCoreState *env, target_ulong arg)
uint32_t helper_abs_h(CPUTriCoreState *env, uint32_t arg)
{
int32_t h, i;
int32_t ovf = 0;
@ -1143,7 +1130,7 @@ uint32_t helper_abs_h(CPUTriCoreState *env, target_ulong arg)
return ret;
}
uint32_t helper_absdif_b(CPUTriCoreState *env, target_ulong r1, target_ulong r2)
uint32_t helper_absdif_b(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int32_t b, i;
int32_t extr_r2;
@ -1167,7 +1154,7 @@ uint32_t helper_absdif_b(CPUTriCoreState *env, target_ulong r1, target_ulong r2)
return ret;
}
uint32_t helper_absdif_h(CPUTriCoreState *env, target_ulong r1, target_ulong r2)
uint32_t helper_absdif_h(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int32_t h, i;
int32_t extr_r2;
@ -1296,7 +1283,7 @@ uint32_t helper_maddr_q(CPUTriCoreState *env, uint32_t r1, uint32_t r2,
return ret & 0xffff0000ll;
}
uint32_t helper_add_b(CPUTriCoreState *env, target_ulong r1, target_ulong r2)
uint32_t helper_add_b(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int32_t b, i;
int32_t extr_r1, extr_r2;
@ -1322,7 +1309,7 @@ uint32_t helper_add_b(CPUTriCoreState *env, target_ulong r1, target_ulong r2)
return ret;
}
uint32_t helper_add_h(CPUTriCoreState *env, target_ulong r1, target_ulong r2)
uint32_t helper_add_h(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int32_t h, i;
int32_t extr_r1, extr_r2;
@ -1451,7 +1438,7 @@ uint32_t helper_msubr_q(CPUTriCoreState *env, uint32_t r1, uint32_t r2,
return ret & 0xffff0000ll;
}
uint32_t helper_sub_b(CPUTriCoreState *env, target_ulong r1, target_ulong r2)
uint32_t helper_sub_b(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int32_t b, i;
int32_t extr_r1, extr_r2;
@ -1477,7 +1464,7 @@ uint32_t helper_sub_b(CPUTriCoreState *env, target_ulong r1, target_ulong r2)
return ret;
}
uint32_t helper_sub_h(CPUTriCoreState *env, target_ulong r1, target_ulong r2)
uint32_t helper_sub_h(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int32_t h, i;
int32_t extr_r1, extr_r2;
@ -1502,7 +1489,7 @@ uint32_t helper_sub_h(CPUTriCoreState *env, target_ulong r1, target_ulong r2)
return ret;
}
uint32_t helper_eq_b(target_ulong r1, target_ulong r2)
uint32_t helper_eq_b(uint32_t r1, uint32_t r2)
{
uint32_t ret, msk;
int32_t i;
@ -1519,7 +1506,7 @@ uint32_t helper_eq_b(target_ulong r1, target_ulong r2)
return ret;
}
uint32_t helper_eq_h(target_ulong r1, target_ulong r2)
uint32_t helper_eq_h(uint32_t r1, uint32_t r2)
{
int32_t ret = 0;
@ -1534,7 +1521,7 @@ uint32_t helper_eq_h(target_ulong r1, target_ulong r2)
return ret;
}
uint32_t helper_eqany_b(target_ulong r1, target_ulong r2)
uint32_t helper_eqany_b(uint32_t r1, uint32_t r2)
{
int32_t i;
uint32_t ret = 0;
@ -1546,7 +1533,7 @@ uint32_t helper_eqany_b(target_ulong r1, target_ulong r2)
return ret;
}
uint32_t helper_eqany_h(target_ulong r1, target_ulong r2)
uint32_t helper_eqany_h(uint32_t r1, uint32_t r2)
{
uint32_t ret;
@ -1556,7 +1543,7 @@ uint32_t helper_eqany_h(target_ulong r1, target_ulong r2)
return ret;
}
uint32_t helper_lt_b(target_ulong r1, target_ulong r2)
uint32_t helper_lt_b(uint32_t r1, uint32_t r2)
{
int32_t i;
uint32_t ret = 0;
@ -1570,7 +1557,7 @@ uint32_t helper_lt_b(target_ulong r1, target_ulong r2)
return ret;
}
uint32_t helper_lt_bu(target_ulong r1, target_ulong r2)
uint32_t helper_lt_bu(uint32_t r1, uint32_t r2)
{
int32_t i;
uint32_t ret = 0;
@ -1584,7 +1571,7 @@ uint32_t helper_lt_bu(target_ulong r1, target_ulong r2)
return ret;
}
uint32_t helper_lt_h(target_ulong r1, target_ulong r2)
uint32_t helper_lt_h(uint32_t r1, uint32_t r2)
{
uint32_t ret = 0;
@ -1599,7 +1586,7 @@ uint32_t helper_lt_h(target_ulong r1, target_ulong r2)
return ret;
}
uint32_t helper_lt_hu(target_ulong r1, target_ulong r2)
uint32_t helper_lt_hu(uint32_t r1, uint32_t r2)
{
uint32_t ret = 0;
@ -1615,7 +1602,7 @@ uint32_t helper_lt_hu(target_ulong r1, target_ulong r2)
}
#define EXTREMA_H_B(name, op) \
uint32_t helper_##name ##_b(target_ulong r1, target_ulong r2) \
uint32_t helper_##name ##_b(uint32_t r1, uint32_t r2) \
{ \
int32_t i, extr_r1, extr_r2; \
uint32_t ret = 0; \
@ -1629,7 +1616,7 @@ uint32_t helper_##name ##_b(target_ulong r1, target_ulong r2) \
return ret; \
} \
\
uint32_t helper_##name ##_bu(target_ulong r1, target_ulong r2)\
uint32_t helper_##name ##_bu(uint32_t r1, uint32_t r2) \
{ \
int32_t i; \
uint32_t extr_r1, extr_r2; \
@ -1644,7 +1631,7 @@ uint32_t helper_##name ##_bu(target_ulong r1, target_ulong r2)\
return ret; \
} \
\
uint32_t helper_##name ##_h(target_ulong r1, target_ulong r2) \
uint32_t helper_##name ##_h(uint32_t r1, uint32_t r2) \
{ \
int32_t extr_r1, extr_r2; \
uint32_t ret = 0; \
@ -1662,7 +1649,7 @@ uint32_t helper_##name ##_h(target_ulong r1, target_ulong r2) \
return ret; \
} \
\
uint32_t helper_##name ##_hu(target_ulong r1, target_ulong r2)\
uint32_t helper_##name ##_hu(uint32_t r1, uint32_t r2) \
{ \
uint32_t extr_r1, extr_r2; \
uint32_t ret = 0; \
@ -1729,7 +1716,7 @@ EXTREMA_H_B(min, <)
#undef EXTREMA_H_B
uint32_t helper_clo_h(target_ulong r1)
uint32_t helper_clo_h(uint32_t r1)
{
uint32_t ret_hw0 = extract32(r1, 0, 16);
uint32_t ret_hw1 = extract32(r1, 16, 16);
@ -1747,7 +1734,7 @@ uint32_t helper_clo_h(target_ulong r1)
return ret_hw0 | (ret_hw1 << 16);
}
uint32_t helper_clz_h(target_ulong r1)
uint32_t helper_clz_h(uint32_t r1)
{
uint32_t ret_hw0 = extract32(r1, 0, 16);
uint32_t ret_hw1 = extract32(r1, 16, 16);
@ -1765,7 +1752,7 @@ uint32_t helper_clz_h(target_ulong r1)
return ret_hw0 | (ret_hw1 << 16);
}
uint32_t helper_cls_h(target_ulong r1)
uint32_t helper_cls_h(uint32_t r1)
{
uint32_t ret_hw0 = extract32(r1, 0, 16);
uint32_t ret_hw1 = extract32(r1, 16, 16);
@ -1783,7 +1770,7 @@ uint32_t helper_cls_h(target_ulong r1)
return ret_hw0 | (ret_hw1 << 16);
}
uint32_t helper_sh(target_ulong r1, target_ulong r2)
uint32_t helper_sh(uint32_t r1, uint32_t r2)
{
int32_t shift_count = sextract32(r2, 0, 6);
@ -1796,7 +1783,7 @@ uint32_t helper_sh(target_ulong r1, target_ulong r2)
}
}
uint32_t helper_sh_h(target_ulong r1, target_ulong r2)
uint32_t helper_sh_h(uint32_t r1, uint32_t r2)
{
int32_t ret_hw0, ret_hw1;
int32_t shift_count;
@ -1816,7 +1803,7 @@ uint32_t helper_sh_h(target_ulong r1, target_ulong r2)
}
}
uint32_t helper_sha(CPUTriCoreState *env, target_ulong r1, target_ulong r2)
uint32_t helper_sha(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int32_t shift_count;
int64_t result, t1;
@ -1854,7 +1841,7 @@ uint32_t helper_sha(CPUTriCoreState *env, target_ulong r1, target_ulong r2)
return ret;
}
uint32_t helper_sha_h(target_ulong r1, target_ulong r2)
uint32_t helper_sha_h(uint32_t r1, uint32_t r2)
{
int32_t shift_count;
int32_t ret_hw0, ret_hw1;
@ -1874,7 +1861,7 @@ uint32_t helper_sha_h(target_ulong r1, target_ulong r2)
}
}
uint32_t helper_bmerge(target_ulong r1, target_ulong r2)
uint32_t helper_bmerge(uint32_t r1, uint32_t r2)
{
uint32_t i, ret;
@ -1905,7 +1892,7 @@ uint64_t helper_bsplit(uint32_t r1)
return ret;
}
uint32_t helper_parity(target_ulong r1)
uint32_t helper_parity(uint32_t r1)
{
uint32_t ret;
uint32_t nOnes, i;
@ -1942,7 +1929,7 @@ uint32_t helper_parity(target_ulong r1)
}
uint32_t helper_pack(uint32_t carry, uint32_t r1_low, uint32_t r1_high,
target_ulong r2)
uint32_t r2)
{
uint32_t ret;
int32_t fp_exp, fp_frac, temp_exp, fp_exp_frac;
@ -1983,7 +1970,7 @@ uint32_t helper_pack(uint32_t carry, uint32_t r1_low, uint32_t r1_high,
return ret;
}
uint64_t helper_unpack(target_ulong arg1)
uint64_t helper_unpack(uint32_t arg1)
{
int32_t fp_exp = extract32(arg1, 23, 8);
int32_t fp_frac = extract32(arg1, 0, 23);
@ -2408,7 +2395,7 @@ uint32_t helper_shuffle(uint32_t arg0, uint32_t arg1)
/* context save area (CSA) related helpers */
static int cdc_increment(target_ulong *psw)
static int cdc_increment(uint32_t *psw)
{
if ((*psw & MASK_PSW_CDC) == 0x7f) {
return 0;
@ -2426,7 +2413,7 @@ static int cdc_increment(target_ulong *psw)
return 0;
}
static int cdc_decrement(target_ulong *psw)
static int cdc_decrement(uint32_t *psw)
{
if ((*psw & MASK_PSW_CDC) == 0x7f) {
return 0;
@ -2442,7 +2429,7 @@ static int cdc_decrement(target_ulong *psw)
return 0;
}
static bool cdc_zero(target_ulong *psw)
static bool cdc_zero(uint32_t *psw)
{
int cdc = *psw & MASK_PSW_CDC;
/* Returns TRUE if PSW.CDC.COUNT == 0 or if PSW.CDC ==
@ -2457,7 +2444,7 @@ static bool cdc_zero(target_ulong *psw)
return count == 0;
}
static void save_context_upper(CPUTriCoreState *env, target_ulong ea)
static void save_context_upper(CPUTriCoreState *env, uint32_t ea)
{
cpu_stl_data(env, ea, env->PCXI);
cpu_stl_data(env, ea+4, psw_read(env));
@ -2477,7 +2464,7 @@ static void save_context_upper(CPUTriCoreState *env, target_ulong ea)
cpu_stl_data(env, ea+60, env->gpr_d[15]);
}
static void save_context_lower(CPUTriCoreState *env, target_ulong ea)
static void save_context_lower(CPUTriCoreState *env, uint32_t ea)
{
cpu_stl_data(env, ea, env->PCXI);
cpu_stl_data(env, ea+4, env->gpr_a[11]);
@ -2497,8 +2484,8 @@ static void save_context_lower(CPUTriCoreState *env, target_ulong ea)
cpu_stl_data(env, ea+60, env->gpr_d[7]);
}
static void restore_context_upper(CPUTriCoreState *env, target_ulong ea,
target_ulong *new_PCXI, target_ulong *new_PSW)
static void restore_context_upper(CPUTriCoreState *env, uint32_t ea,
uint32_t *new_PCXI, uint32_t *new_PSW)
{
*new_PCXI = cpu_ldl_data(env, ea);
*new_PSW = cpu_ldl_data(env, ea+4);
@ -2518,8 +2505,8 @@ static void restore_context_upper(CPUTriCoreState *env, target_ulong ea,
env->gpr_d[15] = cpu_ldl_data(env, ea+60);
}
static void restore_context_lower(CPUTriCoreState *env, target_ulong ea,
target_ulong *ra, target_ulong *pcxi)
static void restore_context_lower(CPUTriCoreState *env, uint32_t ea,
uint32_t *ra, uint32_t *pcxi)
{
*pcxi = cpu_ldl_data(env, ea);
*ra = cpu_ldl_data(env, ea+4);
@ -2541,10 +2528,10 @@ static void restore_context_lower(CPUTriCoreState *env, target_ulong ea,
void helper_call(CPUTriCoreState *env, uint32_t next_pc)
{
target_ulong tmp_FCX;
target_ulong ea;
target_ulong new_FCX;
target_ulong psw;
uint32_t tmp_FCX;
uint32_t ea;
uint32_t new_FCX;
uint32_t psw;
psw = psw_read(env);
/* if (FCX == 0) trap(FCU); */
@ -2604,9 +2591,9 @@ void helper_call(CPUTriCoreState *env, uint32_t next_pc)
void helper_ret(CPUTriCoreState *env)
{
target_ulong ea;
target_ulong new_PCXI;
target_ulong new_PSW, psw;
uint32_t ea;
uint32_t new_PCXI;
uint32_t new_PSW, psw;
psw = psw_read(env);
/* if (PSW.CDE) then if (cdc_decrement()) then trap(CDU);*/
@ -2657,9 +2644,9 @@ void helper_ret(CPUTriCoreState *env)
void helper_bisr(CPUTriCoreState *env, uint32_t const9)
{
target_ulong tmp_FCX;
target_ulong ea;
target_ulong new_FCX;
uint32_t tmp_FCX;
uint32_t ea;
uint32_t new_FCX;
if (env->FCX == 0) {
/* FCU trap */
@ -2701,9 +2688,9 @@ void helper_bisr(CPUTriCoreState *env, uint32_t const9)
void helper_rfe(CPUTriCoreState *env)
{
target_ulong ea;
target_ulong new_PCXI;
target_ulong new_PSW;
uint32_t ea;
uint32_t new_PCXI;
uint32_t new_PSW;
/* if (PCXI[19: 0] == 0) then trap(CSU); */
if ((env->PCXI & 0xfffff) == 0) {
/* raise csu trap */
@ -2762,35 +2749,35 @@ void helper_rfm(CPUTriCoreState *env)
}
}
void helper_ldlcx(CPUTriCoreState *env, target_ulong ea)
void helper_ldlcx(CPUTriCoreState *env, uint32_t ea)
{
uint32_t dummy;
/* insn doesn't load PCXI and RA */
restore_context_lower(env, ea, &dummy, &dummy);
}
void helper_lducx(CPUTriCoreState *env, target_ulong ea)
void helper_lducx(CPUTriCoreState *env, uint32_t ea)
{
uint32_t dummy;
/* insn doesn't load PCXI and PSW */
restore_context_upper(env, ea, &dummy, &dummy);
}
void helper_stlcx(CPUTriCoreState *env, target_ulong ea)
void helper_stlcx(CPUTriCoreState *env, uint32_t ea)
{
save_context_lower(env, ea);
}
void helper_stucx(CPUTriCoreState *env, target_ulong ea)
void helper_stucx(CPUTriCoreState *env, uint32_t ea)
{
save_context_upper(env, ea);
}
void helper_svlcx(CPUTriCoreState *env)
{
target_ulong tmp_FCX;
target_ulong ea;
target_ulong new_FCX;
uint32_t tmp_FCX;
uint32_t ea;
uint32_t new_FCX;
if (env->FCX == 0) {
/* FCU trap */
@ -2831,9 +2818,9 @@ void helper_svlcx(CPUTriCoreState *env)
void helper_svucx(CPUTriCoreState *env)
{
target_ulong tmp_FCX;
target_ulong ea;
target_ulong new_FCX;
uint32_t tmp_FCX;
uint32_t ea;
uint32_t new_FCX;
if (env->FCX == 0) {
/* FCU trap */
@ -2874,8 +2861,8 @@ void helper_svucx(CPUTriCoreState *env)
void helper_rslcx(CPUTriCoreState *env)
{
target_ulong ea;
target_ulong new_PCXI;
uint32_t ea;
uint32_t new_PCXI;
/* if (PCXI[19: 0] == 0) then trap(CSU); */
if ((env->PCXI & 0xfffff) == 0) {
/* CSU trap */

3978
target/tricore/translate.c
View file

File diff suppressed because it is too large Load diff

6
target/xtensa/cpu.c
View file

@ -59,13 +59,13 @@ static TCGTBCPUState xtensa_get_tb_cpu_state(CPUState *cs)
{
CPUXtensaState *env = cpu_env(cs);
uint32_t flags = 0;
target_ulong cs_base = 0;
uint64_t cs_base = 0;
flags |= xtensa_get_ring(env);
if (env->sregs[PS] & PS_EXCM) {
flags |= XTENSA_TBFLAG_EXCM;
} else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) {
target_ulong lend_dist =
uint64_t lend_dist =
env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS));
/*
@ -83,7 +83,7 @@ static TCGTBCPUState xtensa_get_tb_cpu_state(CPUState *cs)
* for the TB that contains this instruction.
*/
if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) {
target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG];
uint64_t lbeg_off = env->sregs[LEND] - env->sregs[LBEG];
cs_base = lend_dist;
if (lbeg_off < 256) {

2
target/xtensa/translate.c
View file

@ -1166,7 +1166,7 @@ static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
CPUXtensaState *env = cpu_env(cpu);
target_ulong page_start;
vaddr page_start;
/* These two conditions only apply to the first insn in the TB,
but this is the first TranslateOps hook that allows exiting. */

11
target/xtensa/xtensa-semi.c
View file

@ -32,6 +32,7 @@
#include "exec/target_page.h"
#include "semihosting/semihost.h"
#include "semihosting/uaccess.h"
#include "system/memory.h"
#include "qapi/error.h"
#include "qemu/log.h"
@ -192,7 +193,9 @@ void xtensa_sim_open_console(Chardev *chr)
void HELPER(simcall)(CPUXtensaState *env)
{
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
CPUState *cs = env_cpu(env);
AddressSpace *as = cs->as;
uint32_t *regs = env->regs;
switch (regs[2]) {
@ -215,7 +218,7 @@ void HELPER(simcall)(CPUXtensaState *env)
TARGET_PAGE_SIZE - (vaddr & (TARGET_PAGE_SIZE - 1));
uint32_t io_sz = page_left < len ? page_left : len;
hwaddr sz = io_sz;
void *buf = cpu_physical_memory_map(paddr, &sz, !is_write);
void *buf = address_space_map(as, paddr, &sz, !is_write, attrs);
uint32_t io_done;
bool error = false;
@ -261,7 +264,7 @@ void HELPER(simcall)(CPUXtensaState *env)
error = true;
io_done = 0;
}
cpu_physical_memory_unmap(buf, sz, !is_write, io_done);
address_space_unmap(as, buf, sz, !is_write, io_done);
} else {
error = true;
regs[3] = TARGET_EINVAL;
@ -408,11 +411,11 @@ void HELPER(simcall)(CPUXtensaState *env)
while (sz) {
hwaddr len = sz;
void *buf = cpu_physical_memory_map(base, &len, 1);
void *buf = address_space_map(as, base, &len, true, attrs);
if (buf && len) {
memset(buf, regs[4], len);
cpu_physical_memory_unmap(buf, len, 1, len);
address_space_unmap(as, buf, len, true, len);
} else {
len = 1;
}