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target/arm: Add AIE to ARMVAParameters

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Allow the bit to be set in TCR2;
extract the bit in aa64_va_parameters.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20251014195017.421681-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2025-10-23 13:12:50 +01:00 • committed by Peter Maydell
parent f50cbc6e6c
commit 3bbdeedd6a
2 changed files with 22 additions and 9 deletions
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30
target/arm/helper.c
View file

@ -6098,6 +6098,9 @@ static void tcr2_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
if (cpu_isar_feature(aa64_s1pie, cpu)) {
valid_mask |= TCR2_PIE;
}
if (cpu_isar_feature(aa64_aie, cpu)) {
valid_mask |= TCR2_AIE;
}
value &= valid_mask;
raw_write(env, ri, value);
}
@ -6111,7 +6114,10 @@ static void tcr2_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
if (cpu_isar_feature(aa64_s1pie, cpu)) {
valid_mask |= TCR2_PIE;
}
if (cpu_isar_feature(aa64_mec, env_archcpu(env))) {
if (cpu_isar_feature(aa64_aie, cpu)) {
valid_mask |= TCR2_AIE;
}
if (cpu_isar_feature(aa64_mec, cpu)) {
valid_mask |= TCR2_AMEC0 | TCR2_AMEC1;
}
value &= valid_mask;
@ -9666,6 +9672,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
{
uint64_t tcr = regime_tcr(env, mmu_idx);
bool epd, hpd, tsz_oob, ds, ha, hd, pie = false;
bool aie = false;
int select, tsz, tbi, max_tsz, min_tsz, ps, sh;
ARMGranuleSize gran;
ARMCPU *cpu = env_archcpu(env);
@ -9688,10 +9695,12 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
if (r_el == 3) {
pie = (extract64(tcr, 35, 1)
&& cpu_isar_feature(aa64_s1pie, cpu));
} else {
pie = ((env->cp15.tcr2_el[2] & TCR2_PIE)
&& (!arm_feature(env, ARM_FEATURE_EL3)
|| (env->cp15.scr_el3 & SCR_TCR2EN)));
aie = (extract64(tcr, 37, 1)
&& cpu_isar_feature(aa64_aie, cpu));
} else if (!arm_feature(env, ARM_FEATURE_EL3)
|| (env->cp15.scr_el3 & SCR_TCR2EN)) {
pie = env->cp15.tcr2_el[2] & TCR2_PIE;
aie = env->cp15.tcr2_el[2] & TCR2_AIE;
}
}
epd = false;
@ -9733,10 +9742,12 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
epd = true;
}
pie = ((env->cp15.tcr2_el[r_el] & TCR2_PIE)
&& (!arm_feature(env, ARM_FEATURE_EL3)
|| (env->cp15.scr_el3 & SCR_TCR2EN))
&& (r_el == 2 || (arm_hcrx_el2_eff(env) & HCRX_TCR2EN)));
if ((!arm_feature(env, ARM_FEATURE_EL3)
|| (env->cp15.scr_el3 & SCR_TCR2EN))
&& (r_el == 2 || (arm_hcrx_el2_eff(env) & HCRX_TCR2EN))) {
pie = env->cp15.tcr2_el[r_el] & TCR2_PIE;
aie = env->cp15.tcr2_el[r_el] & TCR2_AIE;
}
}
hpd |= pie;
@ -9818,6 +9829,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
.hd = ha && hd,
.gran = gran,
.pie = pie,
.aie = aie,
};
}

1
target/arm/internals.h
View file

@ -1391,6 +1391,7 @@ typedef struct ARMVAParameters {
bool hd : 1;
ARMGranuleSize gran : 2;
bool pie : 1;
bool aie : 1;
} ARMVAParameters;
/**