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aspeed queue:

Browse source 
* Fixed typo in the AST2700 LTPI device
 * Fixed missing wiring of the SPI IRQ in AST10x0, AST2600, AST2700 SoCs
 * Updated ASPEED PCIe Root Port capabilities and MSI support
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Merge tag 'pull-aspeed-20251124' of https://github.com/legoater/qemu into staging

aspeed queue:

* Fixed typo in the AST2700 LTPI device
* Fixed missing wiring of the SPI IRQ in AST10x0, AST2600, AST2700 SoCs
* Updated ASPEED PCIe Root Port capabilities and MSI support

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# gpg: Signature made Sun 23 Nov 2025 11:05:00 PM PST
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full]
# gpg:                 aka "Cédric Le Goater <clg@kaod.org>" [full]

* tag 'pull-aspeed-20251124' of https://github.com/legoater/qemu:
  hw/pci-host/aspeed_pcie: Update ASPEED PCIe Root Port capabilities and enable MSI to support hotplug
  hw/arm/aspeed: Fix missing SPI IRQ connection causing DMA interrupt failure
  hw/arm/ast27x0: Fix typo in LTPI address

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-11-24 09:02:22 -08:00
commit 596e4b7bf5
4 changed files with 46 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

2
hw/arm/aspeed_ast10x0.c
View file

@ -372,6 +372,8 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
sc->memmap[ASPEED_DEV_SPI1 + i]);
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1,
ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_SPI1 + i));
}
/* Secure Boot Controller */

2
hw/arm/aspeed_ast2600.c
View file

@ -557,6 +557,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
sc->memmap[ASPEED_DEV_SPI1 + i]);
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1,
ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_SPI1 + i));
}
/* EHCI */

4
hw/arm/aspeed_ast27x0.c
View file

@ -87,11 +87,11 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_UART11] = 0x14C33A00,
[ASPEED_DEV_UART12] = 0x14C33B00,
[ASPEED_DEV_WDT] = 0x14C37000,
[ASPEED_DEV_LTPI] = 0x30000000,
[ASPEED_DEV_PCIE_MMIO0] = 0x60000000,
[ASPEED_DEV_PCIE_MMIO1] = 0x80000000,
[ASPEED_DEV_PCIE_MMIO2] = 0xA0000000,
[ASPEED_DEV_SPI_BOOT] = 0x100000000,
[ASPEED_DEV_LTPI] = 0x300000000,
[ASPEED_DEV_SDRAM] = 0x400000000,
};
@ -831,6 +831,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
sc->memmap[ASPEED_DEV_SPI0 + i]);
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1,
ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_SPI0 + i));
}
/* EHCI */

40
hw/pci-host/aspeed_pcie.c
View file

@ -68,6 +68,38 @@ static const TypeInfo aspeed_pcie_root_device_info = {
* PCIe Root Port
*/
#define ASPEED_PCIE_ROOT_PORT_MSI_OFFSET 0x50
#define ASPEED_PCIE_ROOT_PORT_MSI_NR_VECTOR 1
#define ASPEED_PCIE_ROOT_PORT_SSVID_OFFSET 0xC0
#define ASPEED_PCIE_ROOT_PORT_EXP_OFFSET 0x80
#define ASPEED_PCIE_ROOT_PORT_AER_OFFSET 0x100
static uint8_t aspeed_pcie_root_port_aer_vector(const PCIDevice *d)
{
return 0;
}
static int aspeed_pcie_root_port_interrupts_init(PCIDevice *d, Error **errp)
{
int rc;
rc = msi_init(d, ASPEED_PCIE_ROOT_PORT_MSI_OFFSET,
ASPEED_PCIE_ROOT_PORT_MSI_NR_VECTOR,
PCI_MSI_FLAGS_MASKBIT & PCI_MSI_FLAGS_64BIT,
PCI_MSI_FLAGS_MASKBIT & PCI_MSI_FLAGS_MASKBIT,
errp);
if (rc < 0) {
assert(rc == -ENOTSUP);
}
return rc;
}
static void aspeed_pcie_root_port_interrupts_uninit(PCIDevice *d)
{
msi_uninit(d);
}
static void aspeed_pcie_root_port_class_init(ObjectClass *klass,
const void *data)
{
@ -80,7 +112,13 @@ static void aspeed_pcie_root_port_class_init(ObjectClass *klass,
k->device_id = 0x1150;
dc->user_creatable = true;
rpc->aer_offset = 0x100;
rpc->aer_vector = aspeed_pcie_root_port_aer_vector;
rpc->interrupts_init = aspeed_pcie_root_port_interrupts_init;
rpc->interrupts_uninit = aspeed_pcie_root_port_interrupts_uninit;
rpc->exp_offset = ASPEED_PCIE_ROOT_PORT_EXP_OFFSET;
rpc->aer_offset = ASPEED_PCIE_ROOT_PORT_AER_OFFSET;
rpc->ssvid_offset = ASPEED_PCIE_ROOT_PORT_SSVID_OFFSET;
rpc->ssid = 0x1150;
}
static const TypeInfo aspeed_pcie_root_port_info = {