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target/riscv: Conceal MO_TE within gen_load() / gen_store()

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All callers of gen_load() / gen_store() set the MO_TE flag.
Set it once in the callees.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20251010155045.78220-6-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Philippe Mathieu-Daudé 2025-10-10 17:50:36 +02:00 • committed by Alistair Francis
parent 133080735c
commit 5ed09d6f7b
2 changed files with 16 additions and 14 deletions
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24
target/riscv/insn_trans/trans_rvi.c.inc
View file

@ -402,6 +402,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
{
bool out;
memop |= MO_TE;
if (ctx->cfg_ptr->ext_zama16b) {
memop |= MO_ATOM_WITHIN16;
}
@ -426,24 +427,24 @@ static bool trans_lb(DisasContext *ctx, arg_lb *a)
static bool trans_lh(DisasContext *ctx, arg_lh *a)
{
return gen_load(ctx, a, MO_TE | MO_SW);
return gen_load(ctx, a, MO_SW);
}
static bool trans_lw(DisasContext *ctx, arg_lw *a)
{
return gen_load(ctx, a, MO_TE | MO_SL);
return gen_load(ctx, a, MO_SL);
}
static bool trans_ld(DisasContext *ctx, arg_ld *a)
{
REQUIRE_64_OR_128BIT(ctx);
return gen_load(ctx, a, MO_TE | MO_SQ);
return gen_load(ctx, a, MO_SQ);
}
static bool trans_lq(DisasContext *ctx, arg_lq *a)
{
REQUIRE_128BIT(ctx);
return gen_load(ctx, a, MO_TE | MO_UO);
return gen_load(ctx, a, MO_UO);
}
static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
@ -453,19 +454,19 @@ static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
{
return gen_load(ctx, a, MO_TE | MO_UW);
return gen_load(ctx, a, MO_UW);
}
static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
{
REQUIRE_64_OR_128BIT(ctx);
return gen_load(ctx, a, MO_TE | MO_UL);
return gen_load(ctx, a, MO_UL);
}
static bool trans_ldu(DisasContext *ctx, arg_ldu *a)
{
REQUIRE_128BIT(ctx);
return gen_load(ctx, a, MO_TE | MO_UQ);
return gen_load(ctx, a, MO_UQ);
}
static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop)
@ -503,6 +504,7 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a, MemOp memop)
static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
{
memop |= MO_TE;
if (ctx->cfg_ptr->ext_zama16b) {
memop |= MO_ATOM_WITHIN16;
}
@ -521,24 +523,24 @@ static bool trans_sb(DisasContext *ctx, arg_sb *a)
static bool trans_sh(DisasContext *ctx, arg_sh *a)
{
return gen_store(ctx, a, MO_TE | MO_SW);
return gen_store(ctx, a, MO_SW);
}
static bool trans_sw(DisasContext *ctx, arg_sw *a)
{
return gen_store(ctx, a, MO_TE | MO_SL);
return gen_store(ctx, a, MO_SL);
}
static bool trans_sd(DisasContext *ctx, arg_sd *a)
{
REQUIRE_64_OR_128BIT(ctx);
return gen_store(ctx, a, MO_TE | MO_UQ);
return gen_store(ctx, a, MO_UQ);
}
static bool trans_sq(DisasContext *ctx, arg_sq *a)
{
REQUIRE_128BIT(ctx);
return gen_store(ctx, a, MO_TE | MO_UO);
return gen_store(ctx, a, MO_UO);
}
static bool trans_addd(DisasContext *ctx, arg_addd *a)

6
target/riscv/insn_trans/trans_rvzce.c.inc
View file

@ -88,13 +88,13 @@ static bool trans_c_lbu(DisasContext *ctx, arg_c_lbu *a)
static bool trans_c_lhu(DisasContext *ctx, arg_c_lhu *a)
{
REQUIRE_ZCB(ctx);
return gen_load(ctx, a, MO_TE | MO_UW);
return gen_load(ctx, a, MO_UW);
}
static bool trans_c_lh(DisasContext *ctx, arg_c_lh *a)
{
REQUIRE_ZCB(ctx);
return gen_load(ctx, a, MO_TE | MO_SW);
return gen_load(ctx, a, MO_SW);
}
static bool trans_c_sb(DisasContext *ctx, arg_c_sb *a)
@ -106,7 +106,7 @@ static bool trans_c_sb(DisasContext *ctx, arg_c_sb *a)
static bool trans_c_sh(DisasContext *ctx, arg_c_sh *a)
{
REQUIRE_ZCB(ctx);
return gen_store(ctx, a, MO_TE | MO_UW);
return gen_store(ctx, a, MO_UW);
}
#define X_S0 8