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x86: ich9: fix default value of 'No Reboot' bit in GCS

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[2] initialized 'No Reboot' bit to 1 by default. And due to quirk it happened
to work with linux iTCO_wdt driver (which clears it on module load).

However spec [1] states:
"
R/W. This bit is set when the “No Reboot” strap (SPKR pin on
ICH9) is sampled high on PWROK.
"

So it should be set only when  '-global ICH9-LPC.noreboot=true' and cleared
when it's false (which should be default).

Fix it to behave according to spec and set 'No Reboot' bit only when
'-global ICH9-LPC.noreboot=true'.

1)
Intel I/O Controller Hub 9 (ICH9) Family Datasheet (rev: 004)
2)

Fixes: 920557971b (ich9: add TCO interface emulation)
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-ID: <20250922132600.562193-1-imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Igor Mammedov 2025-09-22 15:26:00 +02:00 • committed by Michael S. Tsirkin
parent 676757e50c
commit b10166b104
2 changed files with 7 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

7
hw/isa/lpc_ich9.c
View file

@ -132,6 +132,11 @@ static void ich9_cc_init(ICH9LPCState *lpc)
static void ich9_cc_reset(ICH9LPCState *lpc)
{
uint8_t *c = lpc->chip_config;
uint32_t gcs = ICH9_CC_GCS_DEFAULT;
if (lpc->pin_strap.spkr_hi) {
gcs |= ICH9_CC_GCS_NO_REBOOT;
}
memset(lpc->chip_config, 0, sizeof(lpc->chip_config));
@ -142,7 +147,7 @@ static void ich9_cc_reset(ICH9LPCState *lpc)
pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT);
pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT);
pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT);
pci_set_long(c + ICH9_CC_GCS, ICH9_CC_GCS_DEFAULT);
pci_set_long(c + ICH9_CC_GCS, gcs);
ich9_cc_update(lpc);
}

2
include/hw/southbridge/ich9.h
View file

@ -95,7 +95,7 @@ struct ICH9LPCState {
#define ICH9_CC_OIC 0x31FF
#define ICH9_CC_OIC_AEN 0x1
#define ICH9_CC_GCS 0x3410
#define ICH9_CC_GCS_DEFAULT 0x00000020
#define ICH9_CC_GCS_DEFAULT 0x00000000
#define ICH9_CC_GCS_NO_REBOOT (1 << 5)
/* D28:F[0-5] */