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wip! sc14445 (sort of 14443, unknown) dummy

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fridtjof 2026-05-13 14:54:07 +02:00
parent 3918b2c050
commit ce117c008f
3 changed files with 103 additions and 0 deletions
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1
hw/cr16c/meson.build
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@ -1,5 +1,6 @@
cr16c_ss = ss.source_set()
cr16c_ss.add(files('virt.c'))
cr16c_ss.add(files('sc14445.c'))
cr16c_ss.add(files('sc14461.c'))
cr16c_ss.add(files('sc14480.c'))
cr16c_ss.add(files('de410.c'))

72
hw/cr16c/sc14445.c Normal file
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#include "sc14445.h"
#include "cpu-qom.h"
#include "system/address-spaces.h"
#include "hw/core/cpu.h"
#include "hw/cr16c/boot.h"
#include "hw/misc/unimp.h"
#include "qapi/error.h"
#include "qemu/datadir.h"
#include "qemu/units.h"
static void sc14445_realize(DeviceState* dev, Error** errp)
{
SC14445McuState* s = SC14445_MCU(dev);
object_initialize_child(OBJECT(dev), "cpu", &s->cpu, TYPE_CR16C_CPU);
object_property_set_bool(OBJECT(&s->cpu), "realized", true, &error_abort);
memory_region_init_ram(&s->non_shared_ram_or_icache, OBJECT(dev), "non_shared_ram_or_icache", 24*KiB, &error_fatal);
memory_region_init_ram(&s->non_shared_ram_or_dcache, OBJECT(dev), "non_shared_ram_or_dcache", 8*KiB, &error_fatal);
memory_region_init_ram(&s->shared_int_ram, OBJECT(dev), "shared_int_ram", 64*KiB, &error_fatal);
memory_region_init_rom(&s->boot_rom, OBJECT(dev), "boot_rom", 2*KiB, &error_fatal);
memory_region_add_subregion(get_system_memory(), 0x00000, &s->non_shared_ram_or_icache);
memory_region_add_subregion(get_system_memory(), 0x08000, &s->non_shared_ram_or_dcache);
memory_region_add_subregion(get_system_memory(), 0x10000, &s->shared_int_ram);
memory_region_add_subregion(get_system_memory(), 0xFEF000, &s->boot_rom);
create_unimplemented_device("mmio", 0xFF0000, 0xFFFBFF - 0xFF0000);
create_unimplemented_device("icu", 0xFFFC00, 0xFFFFFF - 0xFFFC00); // interrupt controller unit
char* bios_path = qemu_find_file(QEMU_FILE_TYPE_BIOS, "sc14445-bios.img");
if (!cr16c_load_firmware(&s->cpu, &s->boot_rom, bios_path)) {
exit(1);
}
}
static void sc14445_reset_hold(Object *obj, ResetType type) {
SC14445McuClass* mcu_class = SC14445_MCU_GET_CLASS(obj);
SC14445McuState* mcu_state = SC14445_MCU(obj);
CR16CCPU* cpu = &mcu_state->cpu;
CPUState* cpu_state = CPU(cpu);
if (mcu_class->parent_phases.hold) {
mcu_class->parent_phases.hold(obj, type);
}
cpu_reset(cpu_state);
cpu_set_pc(cpu_state, 0xFEF000);
}
static void sc14445_class_init(ObjectClass* oc, const void* data)
{
DeviceClass* dc = DEVICE_CLASS(oc);
SC14445McuClass* sc14445 = SC14445_MCU_CLASS(oc);
ResettableClass *rc = RESETTABLE_CLASS(oc);
resettable_class_set_parent_phases(rc, NULL, sc14445_reset_hold, NULL, &sc14445->parent_phases);
dc->realize = sc14445_realize;
}
static const TypeInfo sc14445_mcu_types[] = {
{
.name = TYPE_SC14445_MCU,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SC14445McuState),
.class_size = sizeof(SC14445McuClass),
.class_init = sc14445_class_init,
},
};
DEFINE_TYPES(sc14445_mcu_types)

30
hw/cr16c/sc14445.h Normal file
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#ifndef HW_SC14445_H
#define HW_SC14445_H
#include "cpu.h"
#include "hw/sysbus.h"
#define TYPE_SC14445_MCU "SC14445"
typedef struct SC14445McuState SC14445McuState;
DECLARE_INSTANCE_CHECKER(SC14445McuState, SC14445_MCU, TYPE_SC14445_MCU)
struct SC14445McuState {
SysBusDevice parent_obj;
CR16CCPU cpu;
MemoryRegion non_shared_ram_or_icache;
MemoryRegion non_shared_ram_or_dcache;
MemoryRegion shared_int_ram;
MemoryRegion boot_rom;
};
typedef struct SC14445McuClass {
SysBusDeviceClass parent_class;
ResettablePhases parent_phases;
} SC14445McuClass;
DECLARE_CLASS_CHECKERS(SC14445McuClass, SC14445_MCU, TYPE_SC14445_MCU)
#endif /* HW_SC14445_H */