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Misc HW patches

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- Fix MIPS MVPControl.EVP update
 - Fix qxl_unpack_chunks() chunk size calculation
 - Fix Cadence GEM register mask initialization
 - Fix AddressSpaceDispatch use after free
 - Fix building npcm7xx/npcm8xx bootroms
 - Include missing headers
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Merge tag 'hw-misc-20250729' of https://github.com/philmd/qemu into staging

Misc HW patches

- Fix MIPS MVPControl.EVP update
- Fix qxl_unpack_chunks() chunk size calculation
- Fix Cadence GEM register mask initialization
- Fix AddressSpaceDispatch use after free
- Fix building npcm7xx/npcm8xx bootroms
- Include missing headers

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# gpg: Signature made Tue 29 Jul 2025 07:56:58 EDT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
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* tag 'hw-misc-20250729' of https://github.com/philmd/qemu:
  hw/display/sm501: fix missing error-report.h
  roms/Makefile: fix npcmNxx_bootrom build rules
  system/physmem: fix use-after-free with dispatch
  hw/xen/passthrough: add missing error-report include
  hw/net/cadence_gem: fix register mask initialization
  migration: rename target.c to vfio.c
  hw/vfio/vfio-migration: Remove unnecessary 'qemu/typedefs.h' include
  hw/display/qxl-render: fix qxl_unpack_chunks() chunk size calculation
  target/mips: Only update MVPControl.EVP bit if executed by master VPE

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2025-07-29 10:54:13 -04:00
commit e52966be20
9 changed files with 30 additions and 34 deletions
Download patch file Download diff file Expand all files Collapse all files

1
hw/display/sm501.c
View file

@ -26,6 +26,7 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "hw/usb/hcd-ohci.h"

2
hw/net/cadence_gem.c
View file

@ -1756,6 +1756,7 @@ static void gem_realize(DeviceState *dev, Error **errp)
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
}
gem_init_register_masks(s);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->nic = qemu_new_nic(&net_gem_info, &s->conf,
@ -1776,7 +1777,6 @@ static void gem_init(Object *obj)
DB_PRINT("\n");
gem_init_register_masks(s);
memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s,
"enet", sizeof(s->regs));

1
hw/vfio/vfio-migration-internal.h
View file

@ -13,7 +13,6 @@
#include <linux/vfio.h>
#endif
#include "qemu/typedefs.h"
#include "qemu/notify.h"
/*

1
hw/xen/xen_pt.c
View file

@ -54,6 +54,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include <sys/ioctl.h>
#include "hw/pci/pci.h"

2
migration/meson.build
View file

@ -51,4 +51,4 @@ system_ss.add(when: qatzip, if_true: files('multifd-qatzip.c'))
specific_ss.add(when: 'CONFIG_SYSTEM_ONLY',
if_true: files('ram.c',
'target.c'))
'vfio.c'))

2
migration/target.c → migration/vfio.c
View file

@ -1,5 +1,5 @@
/*
* QEMU live migration - functions that need to be compiled target-specific
* QEMU live migration - VFIO
*
* This work is licensed under the terms of the GNU GPL, version 2
* or (at your option) any later version.

8
roms/Makefile
View file

@ -193,12 +193,12 @@ qboot:
cp qboot/build/bios.bin ../pc-bios/qboot.rom
npcm7xx_bootrom:
$(MAKE) -C vbootrom CROSS_COMPILE=$(arm_cross_prefix)
cp vbootrom/npcm7xx_bootrom.bin ../pc-bios/npcm7xx_bootrom.bin
$(MAKE) -C vbootrom/npcm7xx CROSS_COMPILE=$(arm_cross_prefix)
cp vbootrom/npcm7xx/npcm7xx_bootrom.bin ../pc-bios/npcm7xx_bootrom.bin
npcm8xx_bootrom:
$(MAKE) -C vbootrom CROSS_COMPILE=$(aarch64_cross_prefix)
cp vbootrom/npcm8xx_bootrom.bin ../pc-bios/npcm8xx_bootrom.bin
$(MAKE) -C vbootrom/npcm8xx CROSS_COMPILE=$(aarch64_cross_prefix)
cp vbootrom/npcm8xx/npcm8xx_bootrom.bin ../pc-bios/npcm8xx_bootrom.bin
hppa-firmware:
$(MAKE) -C seabios-hppa parisc

15
system/physmem.c
View file

@ -165,13 +165,11 @@ static bool ram_is_cpr_compatible(RAMBlock *rb);
* CPUAddressSpace: all the information a CPU needs about an AddressSpace
* @cpu: the CPU whose AddressSpace this is
* @as: the AddressSpace itself
* @memory_dispatch: its dispatch pointer (cached, RCU protected)
* @tcg_as_listener: listener for tracking changes to the AddressSpace
*/
typedef struct CPUAddressSpace {
CPUState *cpu;
AddressSpace *as;
struct AddressSpaceDispatch *memory_dispatch;
MemoryListener tcg_as_listener;
} CPUAddressSpace;
@ -692,7 +690,7 @@ address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr orig_addr,
IOMMUTLBEntry iotlb;
int iommu_idx;
hwaddr addr = orig_addr;
AddressSpaceDispatch *d = cpu->cpu_ases[asidx].memory_dispatch;
AddressSpaceDispatch *d = address_space_to_dispatch(cpu->cpu_ases[asidx].as);
for (;;) {
section = address_space_translate_internal(d, addr, &addr, plen, false);
@ -753,7 +751,7 @@ MemoryRegionSection *iotlb_to_section(CPUState *cpu,
{
int asidx = cpu_asidx_from_attrs(cpu, attrs);
CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx];
AddressSpaceDispatch *d = cpuas->memory_dispatch;
AddressSpaceDispatch *d = address_space_to_dispatch(cpuas->as);
int section_index = index & ~TARGET_PAGE_MASK;
MemoryRegionSection *ret;
@ -2780,9 +2778,6 @@ static void tcg_log_global_after_sync(MemoryListener *listener)
static void tcg_commit_cpu(CPUState *cpu, run_on_cpu_data data)
{
CPUAddressSpace *cpuas = data.host_ptr;
cpuas->memory_dispatch = address_space_to_dispatch(cpuas->as);
tlb_flush(cpu);
}
@ -2798,11 +2793,7 @@ static void tcg_commit(MemoryListener *listener)
cpu = cpuas->cpu;
/*
* Defer changes to as->memory_dispatch until the cpu is quiescent.
* Otherwise we race between (1) other cpu threads and (2) ongoing
* i/o for the current cpu thread, with data cached by mmu_lookup().
*
* In addition, queueing the work function will kick the cpu back to
* Queueing the work function will kick the cpu back to
* the main loop, which will end the RCU critical section and reclaim
* the memory data structures.
*

32
target/mips/tcg/system/cp0_helper.c
View file

@ -1562,12 +1562,14 @@ target_ulong helper_dvpe(CPUMIPSState *env)
CPUState *other_cs = first_cpu;
target_ulong prev = env->mvp->CP0_MVPControl;
CPU_FOREACH(other_cs) {
MIPSCPU *other_cpu = MIPS_CPU(other_cs);
/* Turn off all VPEs except the one executing the dvpe. */
if (&other_cpu->env != env) {
other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
mips_vpe_sleep(other_cpu);
if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
CPU_FOREACH(other_cs) {
MIPSCPU *other_cpu = MIPS_CPU(other_cs);
/* Turn off all VPEs except the one executing the dvpe. */
if (&other_cpu->env != env) {
other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
mips_vpe_sleep(other_cpu);
}
}
}
return prev;
@ -1578,15 +1580,17 @@ target_ulong helper_evpe(CPUMIPSState *env)
CPUState *other_cs = first_cpu;
target_ulong prev = env->mvp->CP0_MVPControl;
CPU_FOREACH(other_cs) {
MIPSCPU *other_cpu = MIPS_CPU(other_cs);
if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
CPU_FOREACH(other_cs) {
MIPSCPU *other_cpu = MIPS_CPU(other_cs);
if (&other_cpu->env != env
/* If the VPE is WFI, don't disturb its sleep. */
&& !mips_vpe_is_wfi(other_cpu)) {
/* Enable the VPE. */
other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
mips_vpe_wake(other_cpu); /* And wake it up. */
if (&other_cpu->env != env
/* If the VPE is WFI, don't disturb its sleep. */
&& !mips_vpe_is_wfi(other_cpu)) {
/* Enable the VPE. */
other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
mips_vpe_wake(other_cpu); /* And wake it up. */
}
}
}
return prev;