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target/arm: Add GCS enable and trap levels to DisasContext

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Pipe GCSEnabled, GCSReturnValueCheckEnabled, and CheckGCSSTREnabled
through hflags to the translator.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20251008215613.300150-33-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2025-10-08 14:55:32 -07:00 • committed by Peter Maydell
parent d8bf1761ef
commit e5c79193ec
4 changed files with 50 additions and 0 deletions
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3
target/arm/cpu.h
View file

@ -2475,6 +2475,9 @@ FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1)
FIELD(TBFLAG_A64, AH, 37, 1) /* FPCR.AH */
FIELD(TBFLAG_A64, NEP, 38, 1) /* FPCR.NEP */
FIELD(TBFLAG_A64, ZT0EXC_EL, 39, 2)
FIELD(TBFLAG_A64, GCS_EN, 41, 1)
FIELD(TBFLAG_A64, GCS_RVCEN, 42, 1)
FIELD(TBFLAG_A64, GCSSTR_EL, 43, 2)
/*
* Helpers for using the above. Note that only the A64 accessors use

38
target/arm/tcg/hflags.c
View file

@ -451,6 +451,44 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx));
}
if (cpu_isar_feature(aa64_gcs, env_archcpu(env))) {
/* C.f. GCSEnabled */
if (env->cp15.gcscr_el[el] & GCSCR_PCRSEL) {
switch (el) {
default:
if (!el_is_in_host(env, el)
&& !(arm_hcrx_el2_eff(env) & HCRX_GCSEN)) {
break;
}
/* fall through */
case 2:
if (arm_feature(env, ARM_FEATURE_EL3)
&& !(env->cp15.scr_el3 & SCR_GCSEN)) {
break;
}
/* fall through */
case 3:
DP_TBFLAG_A64(flags, GCS_EN, 1);
break;
}
}
/* C.f. GCSReturnValueCheckEnabled */
if (env->cp15.gcscr_el[el] & GCSCR_RVCHKEN) {
DP_TBFLAG_A64(flags, GCS_RVCEN, 1);
}
/* C.f. CheckGCSSTREnabled */
if (!(env->cp15.gcscr_el[el] & GCSCR_STREN)) {
DP_TBFLAG_A64(flags, GCSSTR_EL, el ? el : 1);
} else if (el == 1
&& EX_TBFLAG_ANY(flags, FGT_ACTIVE)
&& !FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR],
HFGITR_EL2, NGCSSTR_EL1)) {
DP_TBFLAG_A64(flags, GCSSTR_EL, 2);
}
}
if (env->vfp.fpcr & FPCR_AH) {
DP_TBFLAG_A64(flags, AH, 1);
}

3
target/arm/tcg/translate-a64.c
View file

@ -10344,6 +10344,9 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
dc->nv2_mem_be = EX_TBFLAG_A64(tb_flags, NV2_MEM_BE);
dc->fpcr_ah = EX_TBFLAG_A64(tb_flags, AH);
dc->fpcr_nep = EX_TBFLAG_A64(tb_flags, NEP);
dc->gcs_en = EX_TBFLAG_A64(tb_flags, GCS_EN);
dc->gcs_rvcen = EX_TBFLAG_A64(tb_flags, GCS_RVCEN);
dc->gcsstr_el = EX_TBFLAG_A64(tb_flags, GCSSTR_EL);
dc->vec_len = 0;
dc->vec_stride = 0;
dc->cp_regs = arm_cpu->cp_regs;

6
target/arm/tcg/translate.h
View file

@ -166,6 +166,12 @@ typedef struct DisasContext {
bool fpcr_ah;
/* True if FPCR.NEP is 1 (FEAT_AFP scalar upper-element result handling) */
bool fpcr_nep;
/* True if GCSEnabled. */
bool gcs_en;
/* True if GCSReturnValueCheckEnabled. */
bool gcs_rvcen;
/* GCSSTR exception EL or 0 if enabled */
uint8_t gcsstr_el;
/*
* >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
* < 0, set by the current instruction.