Commit graph

102531 commits

Author SHA1 Message Date
Peter Maydell
bf89cf14cd trivial branch pull request 20230314
Update MAINTAINER file
 Fix typo in qemu-options.hx
 -----BEGIN PGP SIGNATURE-----
 
 iQJGBAABCAAwFiEEzS913cjjpNwuT1Fz8ww4vT8vvjwFAmQQe1ESHGxhdXJlbnRA
 dml2aWVyLmV1AAoJEPMMOL0/L748qpwP/i6k8Jhy9YIN9J/+V/XE6i/KM5ce29zZ
 8wV7s7/SRobVCFeD4L44Yb4eyyh+XGPrVPosjkloAhM36lfq+2DBWT7A+qjU8PoG
 3jiRi/pSn+Nc+BtZgKOEWc3FNGjCCBJMXWKOf0XC5djwujth1AEh+VKXyly0GaQx
 5DY50/VyGCYskBDy2Pv1jUHAiCHBprDOKtxGaM8wB0XIajnAE2znT1NIVOfzWHO1
 HqoWT/Mery2jN1/80rAstPyQX4tYo4C1wXFf3kwfjJibM3Vwd8XOpYTUmeGFGCZ5
 DttPzi3gS7ZkEPQsPMKuNt8ayag62NeOgnoRlsjNsWwnqHkVb1QxN5liA1ZgOWtj
 xbsQk1Ko2YUfG1a/W3hq4AgTZRiuSe2/H4K4sV5kMwVgCNci0OL7a1oNP6JloQm+
 MGRr/nP9GwwnZyyF4CLHW5pGntly0T4C2Ij+AytstBL4QbuzxJJx7FugGrRxdiE8
 +odpUGo+21TxR3kLq9W4xrEwz/A5VNnpUdLFGHK6iuNjNdHNa+7umtHwB9YLHbjP
 V9XQv60+nnbVoTUYx+/IrZy4mwB3M853kjNMbOQrlX94PBlEXlk1Ro6PKGSJrzcT
 xSLVfsJynsU/8CjfJttXsNEYDk6DcdBvw/aj14QM96Flcfwal+jy8YnIIguPQp3Z
 /ORSiS2uSWvp
 =75ca
 -----END PGP SIGNATURE-----

Merge tag 'trivial-branch-for-8.0-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging

trivial branch pull request 20230314

Update MAINTAINER file
Fix typo in qemu-options.hx

# -----BEGIN PGP SIGNATURE-----
#
# iQJGBAABCAAwFiEEzS913cjjpNwuT1Fz8ww4vT8vvjwFAmQQe1ESHGxhdXJlbnRA
# dml2aWVyLmV1AAoJEPMMOL0/L748qpwP/i6k8Jhy9YIN9J/+V/XE6i/KM5ce29zZ
# 8wV7s7/SRobVCFeD4L44Yb4eyyh+XGPrVPosjkloAhM36lfq+2DBWT7A+qjU8PoG
# 3jiRi/pSn+Nc+BtZgKOEWc3FNGjCCBJMXWKOf0XC5djwujth1AEh+VKXyly0GaQx
# 5DY50/VyGCYskBDy2Pv1jUHAiCHBprDOKtxGaM8wB0XIajnAE2znT1NIVOfzWHO1
# HqoWT/Mery2jN1/80rAstPyQX4tYo4C1wXFf3kwfjJibM3Vwd8XOpYTUmeGFGCZ5
# DttPzi3gS7ZkEPQsPMKuNt8ayag62NeOgnoRlsjNsWwnqHkVb1QxN5liA1ZgOWtj
# xbsQk1Ko2YUfG1a/W3hq4AgTZRiuSe2/H4K4sV5kMwVgCNci0OL7a1oNP6JloQm+
# MGRr/nP9GwwnZyyF4CLHW5pGntly0T4C2Ij+AytstBL4QbuzxJJx7FugGrRxdiE8
# +odpUGo+21TxR3kLq9W4xrEwz/A5VNnpUdLFGHK6iuNjNdHNa+7umtHwB9YLHbjP
# V9XQv60+nnbVoTUYx+/IrZy4mwB3M853kjNMbOQrlX94PBlEXlk1Ro6PKGSJrzcT
# xSLVfsJynsU/8CjfJttXsNEYDk6DcdBvw/aj14QM96Flcfwal+jy8YnIIguPQp3Z
# /ORSiS2uSWvp
# =75ca
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 14 Mar 2023 13:49:05 GMT
# gpg:                using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg:                issuer "laurent@vivier.eu"
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full]
# gpg:                 aka "Laurent Vivier <laurent@vivier.eu>" [full]
# gpg:                 aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full]
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F  5173 F30C 38BD 3F2F BE3C

* tag 'trivial-branch-for-8.0-pull-request' of https://gitlab.com/laurent_vivier/qemu:
  MAINTAINERS: Remove CXL maintainer Ben Widawsky
  MAINTAINERS: update my email address for the clock framework
  qemu-options.hx: remove stray quote

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-14 14:28:35 +00:00
Markus Armbruster
fcc8f37ca3 MAINTAINERS: Remove CXL maintainer Ben Widawsky
Ben is no longer with intel.  He told me he expected to get back to
CXL, but it's not happening as quickly as he'd like, and that it's
best to remove him as maintainer.  So let's do that.

Thank you for serving as maintainer, Ben!

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20230220212437.1462314-1-armbru@redhat.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-03-14 14:46:38 +01:00
Damien Hedde
1d7e672700 MAINTAINERS: update my email address for the clock framework
Also update mailmap

Signed-off-by: Damien Hedde <damien.hedde@dahe.fr>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-Id: <20230213105227.2357-1-damien.hedde@dahe.fr>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-03-14 14:46:33 +01:00
Peter Maydell
27a03171d0 accel/tcg: Fix NB_MMU_MODES to 16
Balance of the target/ patchset which eliminates tcg_temp_free
 Balance of the target/ patchset which eliminates tcg_const
 -----BEGIN PGP SIGNATURE-----
 
 iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmQPcb0dHHJpY2hhcmQu
 aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV885AgAjDbg1soRBy0THf0X
 CVXmQ4yYyUKAonZBL8Abt9yX01BhLFqEsrju3HiaLNOM9DbwWQ4gdvSrtAZ/K2YG
 d6EvC+rJe79pr58MEEhqO4OO1ymp52amRHtEXva4vcKRNuM9WF5by/Hz2PsZyenG
 ysaLBdddooA9SJeL7xYBMpKWFgUm3C8NzfaRfCBVcG94er9u8RUi0kx+drmOLw0g
 vZ3Hekvi2I8Y5mWqvHeAIOsr8Md9PO3ezWxEteE4qsPNTTRfVD93oSGe9nNCYZTX
 wWU51Vfv9GB6hOylAfMRIeCmkjks/gqLOGElsh1MaVovNDTXS5IKV/HgaLaocJHV
 2P81uQ==
 =FpIY
 -----END PGP SIGNATURE-----

Merge tag 'pull-tcg-20230313' of https://gitlab.com/rth7680/qemu into staging

accel/tcg: Fix NB_MMU_MODES to 16
Balance of the target/ patchset which eliminates tcg_temp_free
Balance of the target/ patchset which eliminates tcg_const

# -----BEGIN PGP SIGNATURE-----
#
# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmQPcb0dHHJpY2hhcmQu
# aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV885AgAjDbg1soRBy0THf0X
# CVXmQ4yYyUKAonZBL8Abt9yX01BhLFqEsrju3HiaLNOM9DbwWQ4gdvSrtAZ/K2YG
# d6EvC+rJe79pr58MEEhqO4OO1ymp52amRHtEXva4vcKRNuM9WF5by/Hz2PsZyenG
# ysaLBdddooA9SJeL7xYBMpKWFgUm3C8NzfaRfCBVcG94er9u8RUi0kx+drmOLw0g
# vZ3Hekvi2I8Y5mWqvHeAIOsr8Md9PO3ezWxEteE4qsPNTTRfVD93oSGe9nNCYZTX
# wWU51Vfv9GB6hOylAfMRIeCmkjks/gqLOGElsh1MaVovNDTXS5IKV/HgaLaocJHV
# 2P81uQ==
# =FpIY
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 13 Mar 2023 18:55:57 GMT
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* tag 'pull-tcg-20230313' of https://gitlab.com/rth7680/qemu: (91 commits)
  tcg: Drop tcg_const_*
  tcg: Drop tcg_const_*_vec
  target/tricore: Use min/max for saturate
  target/ppc: Avoid tcg_const_* in translate.c
  target/ppc: Fix gen_tlbsx_booke206
  target/ppc: Rewrite trans_ADDG6S
  target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc
  target/ppc: Avoid tcg_const_* in fp-impl.c.inc
  target/ppc: Avoid tcg_const_* in vsx-impl.c.inc
  target/ppc: Avoid tcg_const_* in xxeval
  target/ppc: Avoid tcg_const_* in vmx-impl.c.inc
  target/ppc: Avoid tcg_const_i64 in do_vcntmb
  target/m68k: Use tcg_constant_i32 in gen_ea_mode
  target/arm: Avoid tcg_const_ptr in handle_rev
  target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn
  target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn
  target/arm: Avoid tcg_const_* in translate-mve.c
  target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str}
  target/arm: Improve trans_BFCI
  target/arm: Create gen_set_rmode, gen_restore_rmode
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-14 10:09:15 +00:00
John Snow
a234ec311b qemu-options.hx: remove stray quote
Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230202223121.252073-1-jsnow@redhat.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-03-13 18:36:38 +01:00
Peter Maydell
5cfda4ce79 * One more fix for the migration qtest
* Remove the edk2 gitlab-CI job
 * Improve the build-system-alpine CI job
 * Fix emulation of the CHRL/CGHRL s390x instructions
 -----BEGIN PGP SIGNATURE-----
 
 iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmQPLmgRHHRodXRoQHJl
 ZGhhdC5jb20ACgkQLtnXdP5wLbUrlhAAsfqqK5UQodnUTfuu/XitdLaMc31Hbqrt
 aKbKvg/ejL2cMzNC0bTZU1Xv8lx09HEij27Fod5O2z73y25FZIn+7mz8POhSeK0k
 C07mrssaPUzM7OcnFmXrsQ6jRSDJEtMLSiYHly4UKjeokV7YAk9gxjrF2CVPOqg3
 YsZFrY6HZHX3H3Me2rtDKgwxzohfwpVKKZS7oO+yUfRgPdcK0jsIkpBKgQjTfNys
 CNtUH5ULC6IBdigiMAW66rNDetwkhoKyfuNcEmOCBR93v/kSDLJugnVcgJlxwwq+
 8ULr4zBlf3MlmZ5xZlPdZ/7dxfdB2LhSALi476ebnVlHq8TIxsPOVJiJ8K3oqUxP
 OfrLhn7el/qozl+aUhfHtoWfYZ0NI/+qffgXFOca/zi5UyqmTXs5GBjZIEoYUsoW
 Vs9mXyoZelHYn0b3u2ClGMiZjPGACYSTVFQJevNKOTxm4gwGpFK7aH5pmkJpFsJW
 582DXFIFk2Dj0flThAxYcZE2QlnDgglvIaKB5ZuaUyIZeugRMVbO1euqik6WzIFN
 tm8wxRmYi7ao388YXYQd/OFSaYuk5A2AG3cmfev4164z87rtCitOUHa8TPvA5oTL
 /xbJMymKq6yCQpEDEaWQox6Wk1jhEv/Zzg3iT0hv1aVPn79bnPJDmm0me6U1yDLl
 sLco473rMHI=
 =uugc
 -----END PGP SIGNATURE-----

Merge tag 'pull-request-2023-03-13' of https://gitlab.com/thuth/qemu into staging

* One more fix for the migration qtest
* Remove the edk2 gitlab-CI job
* Improve the build-system-alpine CI job
* Fix emulation of the CHRL/CGHRL s390x instructions

# -----BEGIN PGP SIGNATURE-----
#
# iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmQPLmgRHHRodXRoQHJl
# ZGhhdC5jb20ACgkQLtnXdP5wLbUrlhAAsfqqK5UQodnUTfuu/XitdLaMc31Hbqrt
# aKbKvg/ejL2cMzNC0bTZU1Xv8lx09HEij27Fod5O2z73y25FZIn+7mz8POhSeK0k
# C07mrssaPUzM7OcnFmXrsQ6jRSDJEtMLSiYHly4UKjeokV7YAk9gxjrF2CVPOqg3
# YsZFrY6HZHX3H3Me2rtDKgwxzohfwpVKKZS7oO+yUfRgPdcK0jsIkpBKgQjTfNys
# CNtUH5ULC6IBdigiMAW66rNDetwkhoKyfuNcEmOCBR93v/kSDLJugnVcgJlxwwq+
# 8ULr4zBlf3MlmZ5xZlPdZ/7dxfdB2LhSALi476ebnVlHq8TIxsPOVJiJ8K3oqUxP
# OfrLhn7el/qozl+aUhfHtoWfYZ0NI/+qffgXFOca/zi5UyqmTXs5GBjZIEoYUsoW
# Vs9mXyoZelHYn0b3u2ClGMiZjPGACYSTVFQJevNKOTxm4gwGpFK7aH5pmkJpFsJW
# 582DXFIFk2Dj0flThAxYcZE2QlnDgglvIaKB5ZuaUyIZeugRMVbO1euqik6WzIFN
# tm8wxRmYi7ao388YXYQd/OFSaYuk5A2AG3cmfev4164z87rtCitOUHa8TPvA5oTL
# /xbJMymKq6yCQpEDEaWQox6Wk1jhEv/Zzg3iT0hv1aVPn79bnPJDmm0me6U1yDLl
# sLco473rMHI=
# =uugc
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 13 Mar 2023 14:08:40 GMT
# gpg:                using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg:                issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg:                 aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg:                 aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg:                 aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3  EAB9 2ED9 D774 FE70 2DB5

* tag 'pull-request-2023-03-13' of https://gitlab.com/thuth/qemu:
  tests/tcg/s390x: Add C(G)HRL test
  target/s390x: Fix emulation of C(G)HRL
  gitlab-ci.d/buildtest: Rework the target list of build-system-alpine
  gitlab-ci: Remove job building EDK2 firmware binaries
  tests/migration: Tweek auto converge limits check

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-13 17:09:33 +00:00
Richard Henderson
0c8b6b9a63 tcg: Drop tcg_const_*
These functions are no longer used.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 07:03:39 -07:00
Richard Henderson
f6ff9c2f8e tcg: Drop tcg_const_*_vec
Replace with tcg_constant_vec*.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 07:03:39 -07:00
Richard Henderson
5a48476ec0 target/tricore: Use min/max for saturate
Use tcg_constant_i32 for the bounds.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 07:03:39 -07:00
Richard Henderson
7058ff5231 target/ppc: Avoid tcg_const_* in translate.c
All remaining uses are strictly read-only.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 07:03:39 -07:00
Richard Henderson
9d15d8e1bb target/ppc: Fix gen_tlbsx_booke206
Fix incorrect read from rD.
Avoid adding 0 when rA == 0.

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 07:03:39 -07:00
Richard Henderson
4fe0e9db0a target/ppc: Rewrite trans_ADDG6S
Compute all carry bits in parallel instead of a loop.

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 07:03:39 -07:00
Richard Henderson
a88c0cfadf target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc
All uses are strictly read-only.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 07:03:39 -07:00
Richard Henderson
61d4bf3338 target/ppc: Avoid tcg_const_* in fp-impl.c.inc
All uses are strictly read-only.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 07:03:39 -07:00
Richard Henderson
36052a7aa9 target/ppc: Avoid tcg_const_* in vsx-impl.c.inc
All remaining uses are strictly read-only.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 07:03:39 -07:00
Richard Henderson
06c005f65c target/ppc: Avoid tcg_const_* in xxeval
Initialize a new temp instead of tcg_const_*.
Fix a pasto in a comment.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 07:03:39 -07:00
Richard Henderson
4528d720b4 target/ppc: Avoid tcg_const_* in vmx-impl.c.inc
All remaining uses are strictly read-only.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 07:03:39 -07:00
Richard Henderson
ffc0ce24fd target/ppc: Avoid tcg_const_i64 in do_vcntmb
Compute both partial results separately and accumulate
at the end, instead of accumulating in the middle.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 07:03:39 -07:00
Richard Henderson
999b7c2659 target/m68k: Use tcg_constant_i32 in gen_ea_mode
Return a constant for an immediate input.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 07:03:39 -07:00
Richard Henderson
56649fd949 target/arm: Avoid tcg_const_ptr in handle_rev
Here it is not trivial to notice first initialization, so explicitly
zero the temps.  Use an array for the output, rather than separate
tcg_rd/tcg_rd_hi variables.

Fixes a bug by adding a missing clear_vec_high.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 07:03:39 -07:00
Richard Henderson
1b7bc9b5c8 target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn
It is easy enough to use mov instead of or-with-zero
and relying on the optimizer to fold away the or.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 07:03:39 -07:00
Richard Henderson
a2c4fb8cae target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn
It is easy enough to use mov instead of or-with-zero and relying
on the optimizer to fold away the or.  Use an array for the output,
rather than separate tcg_res{l,h} variables.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 07:03:39 -07:00
Richard Henderson
063e6e4527 target/arm: Avoid tcg_const_* in translate-mve.c
All uses are in the context of an accumulator conditionally
having a zero input.  Split the rda variable to rda_{i,o},
and set rda_i to tcg_constant_foo(0) when required.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 07:03:39 -07:00
Richard Henderson
d6840b9878 target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str}
This hides the implicit initialization of a variable.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 07:03:39 -07:00
Richard Henderson
3351889caa target/arm: Improve trans_BFCI
Reorg temporary usage so that we can use tcg_constant_i32.
tcg_gen_deposit_i32 already has a width == 32 special case,
so remove the check here.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 07:03:34 -07:00
Richard Henderson
8d1b02a6a1 target/arm: Create gen_set_rmode, gen_restore_rmode
Split out common subroutines for handing rounding mode
changes during translation.  Use tcg_constant_i32 and
tcg_temp_new_i32 instead of tcg_const_i32.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 06:44:38 -07:00
Richard Henderson
97584f2bc8 target/arm: Consistently use ARMFPRounding during translation
In preparation for extracting new helpers, ensure that
the rounding mode is represented as ARMFPRounding and
not FloatRoundMode.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 06:44:38 -07:00
Richard Henderson
6ce21abd40 target/arm: Improve arm_rmode_to_sf
Use proper enumeration types for input and output.
Use a const array to perform the mapping, with an
assert that the input is valid.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 06:44:38 -07:00
Richard Henderson
ab9ced73fa target/arm: Handle FPROUNDING_ODD in arm_rmode_to_sf
While this enumerator has been present since the first commit,
it isn't ever used.  The first actual use of round-to-odd came
with SVE, which currently uses float_round_to_odd instead of
the arm-specific enumerator.

Amusingly, the comment about unhandled TIEAWAY has been
out of date since the initial commit of translate-a64.c.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 06:44:38 -07:00
Richard Henderson
0b29090a68 target/arm: Use rmode >= 0 for need_rmode
Initialize rmode to -1 instead of keeping two variables.
This is already used elsewhere in translate-a64.c.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 06:44:38 -07:00
Richard Henderson
f04de891b5 tcg: Replace tcg_const_i64 in tcg-op.c
These three instances got missed in previous conversion.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 06:44:38 -07:00
Richard Henderson
151293c2fb target/tricore: Avoid tcg_const_i32
All remaining uses are strictly read-only.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 06:44:38 -07:00
Richard Henderson
32f948afcf target/tricore: Drop some temp initialization
The temp variables here are always set afterward;
the initialization with a constant was discarded.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 06:44:38 -07:00
Richard Henderson
0a47678626 target/tricore: Use setcondi instead of explicit allocation
This removes the only use of temp.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 06:44:37 -07:00
Richard Henderson
5c48ad758d target/tricore: Rename t_off10 and use tcg_constant_i32
While temp3 could simply be initialized with tcg_constant_i32,
the renaming makes the purpose clearer.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 06:44:37 -07:00
Richard Henderson
bf38ca5c9e target/tricore: Split t_n as constant from temp as variable
As required, allocate temp separately.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 06:44:37 -07:00
Richard Henderson
905a83dedf tcg/sparc: Avoid tcg_const_tl in gen_edge
Push tcg_constant_tl into the shift argument directly.
Since t1 no longer exists as a temp, replace with lo1,
whose last use was just above.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 06:44:37 -07:00
Richard Henderson
950b91be98 target/sh4: Avoid tcg_const_i32
All remaining uses are strictly read-only.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 06:44:37 -07:00
Richard Henderson
d3c2b2b366 target/sh4: Avoid tcg_const_i32 for TAS.B
Since we're assigning to cpu_sr_t in the end,
use that as the intermediate temp as well.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 06:44:37 -07:00
Richard Henderson
5bd9790ebc target/s390x: Avoid tcg_const_i64
All uses are strictly read-only.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 06:44:37 -07:00
Richard Henderson
daefc08567 target/rx: Avoid tcg_const_i32
All remaining uses are strictly read-only.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 06:44:37 -07:00
Richard Henderson
09374ee274 target/rx: Avoid tcg_const_i32 when new temp needed
These three cases use a constant as first input, and
then overwrite the temp in the output.  Separate them.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 06:44:37 -07:00
Richard Henderson
bb09b540c4 target/rx: Use cpu_psw_z as temp in flags computation
Since PSW_Z = PSW_S, we can move that assignment to the end
and use PSW_Z as a temporary while computing PSW_O.
Use tcg_constant_i32 instead of tcg_const_i32.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 06:44:37 -07:00
Richard Henderson
4b01ff2561 target/rx: Use tcg_gen_abs_i32
Remove the local definition of rx_abs.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 06:44:37 -07:00
Richard Henderson
c3be8116d9 target/ppc: Avoid tcg_const_i64 in do_vector_shift_quad
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 06:44:37 -07:00
Richard Henderson
5b7a8b81d2 target/ppc: Split out gen_vx_vmul10
Move the body out of this large macro.
Use tcg_constant_i64.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 06:44:37 -07:00
Richard Henderson
c29e79af27 target/mips: Avoid tcg_const_* throughout
All remaining uses are strictly read-only.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 06:44:37 -07:00
Richard Henderson
0bcc6b4cfd target/mips: Avoid tcg_const_tl in gen_r6_ld
Allocate a separate temp for modification.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 06:44:37 -07:00
Richard Henderson
0694cd597d target/mips: Split out gen_lxr
Common subroutine for LDR and LWR.
Use tcg_constant_tl of ~1 instead of tcg_const_tl of 0x..fe.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 06:44:37 -07:00
Richard Henderson
990c162e67 target/mips: Split out gen_lxl
Common subroutine for LDL and LWL.
Use tcg_constant_tl instead of tcg_const_tl and t2.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13 06:44:37 -07:00