a1f44e0c59
Add a regression test to verify that MEPC properly masks the lower bits when an address with mode bits is written to it, as required by the RISC-V Privileged Architecture specification. The test sets STVEC to an address with bit 0 set (vectored mode), triggers an illegal instruction exception, copies STVEC to MEPC in the trap handler, and verifies that MEPC masks bits [1:0] correctly for IALIGN=32. Without the fix, MEPC retains the mode bits (returns non-zero/FAIL). With the fix, MEPC clears bits [1:0] (returns 0/PASS). Signed-off-by: Charalampos Mitrodimas <charmitro@posteo.net> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250703182157.281320-3-charmitro@posteo.net> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
28 lines
655 B
Text
28 lines
655 B
Text
#
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# RISC-V system tests
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#
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TEST_SRC = $(SRC_PATH)/tests/tcg/riscv64
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VPATH += $(TEST_SRC)
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LINK_SCRIPT = $(TEST_SRC)/semihost.ld
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LDFLAGS = -T $(LINK_SCRIPT)
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CFLAGS += -g -Og
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%.o: %.S
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$(CC) $(CFLAGS) $< -Wa,--noexecstack -c -o $@
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%: %.o $(LINK_SCRIPT)
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$(LD) $(LDFLAGS) $< -o $@
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QEMU_OPTS += -M virt -display none -semihosting -device loader,file=
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EXTRA_RUNS += run-issue1060
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run-issue1060: issue1060
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$(call run-test, $<, $(QEMU) $(QEMU_OPTS)$<)
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EXTRA_RUNS += run-test-mepc-masking
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run-test-mepc-masking: test-mepc-masking
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$(call run-test, $<, $(QEMU) $(QEMU_OPTS)$<)
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# We don't currently support the multiarch system tests
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undefine MULTIARCH_TESTS
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