688a3dae78
Introduce a QEMU device model for ASPEED's One-Time Programmable (OTP) memory. This model simulates a word-addressable OTP region used for secure fuse storage. The OTP memory can operate with an internal memory buffer. The OTP model provides a memory-like interface through a dedicated AddressSpace, allowing other device models (e.g., SBC) to issue transactions as if accessing a memory-mapped region. Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250812094011.2617526-2-kane_chen@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
33 lines
581 B
C
33 lines
581 B
C
/*
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* ASPEED OTP (One-Time Programmable) memory
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*
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* Copyright (C) 2025 Aspeed
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef ASPEED_OTP_H
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#define ASPEED_OTP_H
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#include "system/memory.h"
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#include "hw/block/block.h"
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#include "system/address-spaces.h"
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#define TYPE_ASPEED_OTP "aspeed-otp"
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OBJECT_DECLARE_SIMPLE_TYPE(AspeedOTPState, ASPEED_OTP)
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typedef struct AspeedOTPState {
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DeviceState parent_obj;
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BlockBackend *blk;
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uint64_t size;
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AddressSpace as;
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MemoryRegion mmio;
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uint8_t *storage;
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} AspeedOTPState;
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#endif /* ASPEED_OTP_H */
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