137 lines
4 KiB
C
137 lines
4 KiB
C
#ifndef QEMU_CR16C_CPU_H
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#define QEMU_CR16C_CPU_H
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#include "qemu/osdep.h"
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#include "cpu-qom.h"
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#include "exec/cpu-defs.h"
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#include "hw/registerfields.h"
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/* PSR define */
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REG16(PSR, 0)
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FIELD(PSR, C, 0, 1)
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FIELD(PSR, T, 1, 1)
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FIELD(PSR, L, 2, 1)
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FIELD(PSR, U, 3, 1)
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// bit 4 is reserved
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FIELD(PSR, F, 5, 1)
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FIELD(PSR, Z, 6, 1)
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FIELD(PSR, N, 7, 1)
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// bit 8 is reserved
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FIELD(PSR, E, 9, 1)
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FIELD(PSR, P, 10, 1)
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FIELD(PSR, I, 11, 1)
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// 12-15 are reserved as well
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/* CFG define */
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REG16(CFG, 0)
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// bit 0, 1 are fixed 0
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FIELD(CFG, DC, 2, 1)
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FIELD(CFG, LDC, 3, 1)
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FIELD(CFG, IC, 4, 1)
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FIELD(CFG, LIC, 5, 1)
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// bit 6, 7 are fixed 0
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FIELD(CFG, ED, 8, 1)
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FIELD(CFG, SR, 9, 1)
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// bit 10-15 are reserved
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#define CR16C_REG_COUNT 16
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#define CR16C_FIRST_32B_REG 12
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#define CR16C_REGNO_RA 14
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#define CR16C_REGNO_SP 15
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#define CPU_RESOLVING_TYPE TYPE_CR16C_CPU
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// TODO: Interrupt mask?
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// TODO: Instruction mask?
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static const char cr16c_cpu_r_names[CR16C_REG_COUNT][8] = {
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "ra", "sp"
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};
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typedef struct CPUArchState {
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uint32_t pc;
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uint32_t r[CR16C_REG_COUNT]; /* General purpose registers: 12x16-bit + 2x32-bit */
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uint32_t psr_n; // Negative bit
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uint32_t psr_z; // Zero bit
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uint32_t psr_f; // Flag bit
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uint32_t psr_l; // Low flag bit
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uint32_t psr_c; // Carry bit
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uint32_t psr_t; // Trace bit
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uint32_t psr_u; // User mode bit
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uint32_t psr_e; // local maskable interrupt Enable bit
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uint32_t psr_p; // trace trap Pending bit
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uint32_t psr_i; // global maskable Interrupt enable bit
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uint32_t cfg_dc; // Data Cache bit
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uint32_t cfg_ldc; // Lock Data Cache bit
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uint32_t cfg_ic; // Instruction Cache bit
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uint32_t cfg_lic; // Lock Instruction Cache bit
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uint32_t cfg_ed; // Extended Dispatch bit
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uint32_t cfg_sr; // Short Register bit
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} CPUCR16CState;
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struct ArchCPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUCR16CState env;
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};
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int cr16c_print_insn(bfd_vma addr, disassemble_info *info);
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static inline int cpu_interrupts_enabled(CPUCR16CState* env) {
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return false; // TODO: Interrupts
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}
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void cr16c_translate_init(void);
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bool cr16c_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr);
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void cr16c_cpu_do_interrupt(CPUState *cpu);
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void cr16c_cpu_setint(void *opaque, int irq, int level);
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hwaddr cr16c_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);
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int cr16c_cpu_memory_rw_debug(CPUState *cs, vaddr addr, uint8_t *buf, int len, bool is_write);
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void cr16c_debug_dump_state(CPUState *cs);
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void cr16c_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
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void cr16c_translate_code(CPUState *cs, TranslationBlock *tb,
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int *max_insns, vaddr pc, void *host_pc);
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void cr16c_restore_state_to_opc(CPUState *cpu, const TranslationBlock *tb,
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const uint64_t *data);
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static inline uint32_t cr16c_cpu_pack_psr(const CPUCR16CState *env)
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{
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uint32_t psr = 0;
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psr = FIELD_DP32(psr, PSR, C, env->psr_c);
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psr = FIELD_DP32(psr, PSR, T, env->psr_t);
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psr = FIELD_DP32(psr, PSR, L, env->psr_l);
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psr = FIELD_DP32(psr, PSR, U, env->psr_u);
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psr = FIELD_DP32(psr, PSR, N, env->psr_n);
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psr = FIELD_DP32(psr, PSR, Z, env->psr_z);
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psr = FIELD_DP32(psr, PSR, F, env->psr_f);
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psr = FIELD_DP32(psr, PSR, E, env->psr_e);
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psr = FIELD_DP32(psr, PSR, P, env->psr_p);
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psr = FIELD_DP32(psr, PSR, I, env->psr_i);
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return psr;
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}
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static inline uint32_t cr16c_cpu_pack_cfg(const CPUCR16CState *env)
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{
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uint32_t cfg = 0;
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cfg = FIELD_DP32(cfg, CFG, DC, env->cfg_dc);
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cfg = FIELD_DP32(cfg, CFG, LDC, env->cfg_ldc);
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cfg = FIELD_DP32(cfg, CFG, IC, env->cfg_ic);
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cfg = FIELD_DP32(cfg, CFG, LIC, env->cfg_lic);
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cfg = FIELD_DP32(cfg, CFG, ED, env->cfg_ed);
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cfg = FIELD_DP32(cfg, CFG, SR, env->cfg_sr);
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return cfg;
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}
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#endif // !QEMU_CR16C_CPU_H
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