qemu-cr16/target
Xin Wang 27535e9cca target/i386: Add support for save/load of exception error code
For now, qemu save/load CPU exception info(such as exception_nr and
has_error_code), while the exception error_code is ignored. This will
cause the dest hypervisor reinject a vCPU exception with error_code(0),
potentially causing a guest kernel panic.

For instance, if src VM stopped with an user-mode write #PF (error_code 6),
the dest hypervisor will reinject an #PF with error_code(0) when vCPU resume,
then guest kernel panic as:
  BUG: unable to handle page fault for address: 00007f80319cb010
  #PF: supervisor read access in user mode
  #PF: error_code(0x0000) - not-present page
  RIP: 0033:0x40115d

To fix it, support save/load exception error_code.

Signed-off-by: Xin Wang <wangxinxin.wang@huawei.com>
Link: https://lore.kernel.org/r/20250819145834.3998-1-wangxinxin.wang@huawei.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-08-20 22:47:43 +02:00
..
alpha target/alpha: Add GDB XML feature file 2025-07-14 11:42:49 +01:00
arm target/arm: Fix handling of setting SVE registers from gdb 2025-08-01 16:48:50 +01:00
avr target: Use cpu_pointer_wrap_uint32 for 32-bit targets 2025-05-28 08:08:48 +01:00
hexagon accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
hppa target: Use cpu_pointer_wrap_notreached for strict align targets 2025-05-28 08:08:47 +01:00
i386 target/i386: Add support for save/load of exception error code 2025-08-20 22:47:43 +02:00
loongarch target/loongarch: Fix [X]VLDI raising exception incorrectly 2025-08-08 09:18:44 +08:00
m68k target: Use cpu_pointer_wrap_uint32 for 32-bit targets 2025-05-28 08:08:48 +01:00
microblaze target: Use cpu_pointer_wrap_uint32 for 32-bit targets 2025-05-28 08:08:48 +01:00
mips target/mips: Only update MVPControl.EVP bit if executed by master VPE 2025-07-29 13:56:15 +02:00
openrisc target: Use cpu_pointer_wrap_uint32 for 32-bit targets 2025-05-28 08:08:48 +01:00
ppc qemu: Declare all load/store helper in 'qemu/bswap.h' 2025-07-15 02:56:39 -04:00
riscv target/riscv: Restrict midelegh access to S-mode harts 2025-07-30 10:59:26 +10:00
rx target: Use cpu_pointer_wrap_uint32 for 32-bit targets 2025-05-28 08:08:48 +01:00
s390x target/s390x: Have s390_cpu_halt() not return anything 2025-07-11 10:33:56 +02:00
sh4 target: Use cpu_pointer_wrap_notreached for strict align targets 2025-05-28 08:08:47 +01:00
sparc gdbstub: add the GDB register XML files for sparc64. 2025-07-14 11:42:49 +01:00
tricore target: Use cpu_pointer_wrap_uint32 for 32-bit targets 2025-05-28 08:08:48 +01:00
xtensa target/xtensa: replace FSF postal address with licenses URL 2025-06-26 00:42:37 +02:00
Kconfig
meson.build