qemu-cr16/target
Daniel Henrique Barboza e06d209aa6 target/riscv: implement MonitorDef HMP API
The MonitorDef API is related to two HMP monitor commands: 'p' and 'x':

(qemu) help p
print|p /fmt expr -- print expression value (use $reg for CPU register access)
(qemu) help x
x /fmt addr -- virtual memory dump starting at 'addr'

For x86, one of the few targets that implements it, it is possible to
print the PC register value with $pc and use the PC value in the 'x'
command as well.

Those 2 commands are hooked into get_monitor_def(), called by
exp_unary() in hmp.c. The function tries to fetch a reg value in two
ways: by reading them directly via a target_monitor_defs array or using
a target_get_monitor_def() helper. In RISC-V we have *A LOT* of
registers and this number will keep getting bigger, so we're opting out
of an array declaration.

We're able to retrieve all regs but vregs because the API only fits an
uint64_t and vregs have 'vlen' size that are bigger than that.

With this patch we can do things such as:

- print CSRs and use their val in expressions:
(qemu) p $mstatus
0xa000000a0
(qemu) p $mstatus & 0xFF
0xa0

- dump the next 10 insn from virtual memory starting at x1 (ra):

(qemu) x/10i $ra
0xffffffff80958aea:  a9bff0ef          jal                     ra,-1382                # 0xffffffff80958584
0xffffffff80958aee:  10016073          csrrsi                  zero,sstatus,2
0xffffffff80958af2:  60a2              ld                      ra,8(sp)
0xffffffff80958af4:  6402              ld                      s0,0(sp)
0xffffffff80958af6:  0141              addi                    sp,sp,16
0xffffffff80958af8:  8082              ret
0xffffffff80958afa:  10016073          csrrsi                  zero,sstatus,2
0xffffffff80958afe:  8082              ret
0xffffffff80958b00:  1141              addi                    sp,sp,-16
0xffffffff80958b02:  e422              sd                      s0,8(sp)
(qemu)

Suggested-by: Dr. David Alan Gilbert <dave@treblig.org>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250703130815.1592493-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-10-02 15:08:36 +10:00
..
alpha target/alpha: Simplify call_pal implementation 2025-09-24 10:29:43 -07:00
arm target-arm queue: 2025-09-26 13:27:01 -07:00
avr treewide: clear bits of cs->interrupt_request with cpu_reset_interrupt() 2025-09-17 19:00:55 +02:00
hexagon accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
hppa target/hppa: Adjust mmu indexes to begin with 0 2025-09-23 16:55:36 -07:00
i386 i386/kvm: Drop KVM_CAP_X86_SMM check in kvm_arch_init() 2025-09-17 19:01:55 +02:00
loongarch loongarch queue 2025-09-28 09:01:35 -07:00
m68k add cpu_test_interrupt()/cpu_set_interrupt() helpers and use them tree wide 2025-08-29 12:48:14 +02:00
microblaze add cpu_test_interrupt()/cpu_set_interrupt() helpers and use them tree wide 2025-08-29 12:48:14 +02:00
mips target/mips: fix TLB huge page check to use 64-bit shift 2025-09-02 17:57:05 +02:00
openrisc treewide: clear bits of cs->interrupt_request with cpu_reset_interrupt() 2025-09-17 19:00:55 +02:00
ppc target/ppc: use MAKE_64BIT_MASK for mcrfs exception clear mask 2025-09-28 23:50:36 +05:30
riscv target/riscv: implement MonitorDef HMP API 2025-10-02 15:08:36 +10:00
rx treewide: clear bits of cs->interrupt_request with cpu_reset_interrupt() 2025-09-17 19:00:55 +02:00
s390x treewide: clear bits of cs->interrupt_request with cpu_reset_interrupt() 2025-09-17 19:00:55 +02:00
sh4 add cpu_test_interrupt()/cpu_set_interrupt() helpers and use them tree wide 2025-08-29 12:48:14 +02:00
sparc target/sparc: Relax decode of rs2_or_imm for v7 2025-09-23 16:51:36 -07:00
tricore target: Use cpu_pointer_wrap_uint32 for 32-bit targets 2025-05-28 08:08:48 +01:00
xtensa target/xtensa: replace FSF postal address with licenses URL 2025-06-26 00:42:37 +02:00
Kconfig target/cris: Remove the deprecated CRIS target 2024-09-13 20:11:13 +02:00
meson.build target/cris: Remove the deprecated CRIS target 2024-09-13 20:11:13 +02:00