Anton Johansson 7dbe2d7df0 hw/riscv: Widen OpenSBI dynamic info struct ... Since fw_dynamic_info is only used for non 32 bit targets, target_long is int64_t anyway. Rename struct to fw_dynamic_info64 and use int64_t. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20251027-feature-single-binary-hw-v1-v2-3-44478d589ae9@rev.ng> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>		2025-10-28 08:19:18 +01:00
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boot.h	hw/riscv: Use generic hwaddr for firmware addresses	2025-10-28 08:19:18 +01:00
boot_opensbi.h	hw/riscv: Widen OpenSBI dynamic info struct	2025-10-28 08:19:18 +01:00
iommu.h	qom: remove redundant typedef when use OBJECT_DECLARE_SIMPLE_TYPE	2025-10-28 08:08:04 +01:00
microchip_pfsoc.h	hw/riscv: Configurable MPFS CLINT timebase freq	2025-05-19 13:30:24 +10:00
numa.h	include: Rename sysemu/ -> system/	2024-12-20 17:44:56 +01:00
opentitan.h	hw/riscv/opentitan: Correct OpenTitanState parent type/size	2023-06-13 17:19:42 +10:00
riscv_hart.h	target/riscv: Handle Smrnmi interrupt and exception	2025-01-19 09:44:34 +10:00
shakti_c.h	hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0	2023-01-06 10:42:55 +10:00
sifive_cpu.h	riscv: Add a sifive_cpu.h to include both E and U cpu type defines	2019-09-17 08:42:46 -07:00
sifive_e.h	hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b.	2023-07-10 22:29:15 +10:00
sifive_u.h	hw/riscv: Move the dtb load bits outside of create_fdt()	2023-03-01 17:19:14 -08:00
spike.h	hw/riscv/spike: use 'fdt' from MachineState	2023-01-20 10:14:13 +10:00
virt.h	hw/riscv/virt: Add the BDF of IOMMU to RISCVVirtState structure	2025-05-19 11:07:13 +10:00
xiangshan_kmh.h	hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototype	2025-07-04 21:09:49 +10:00