f64cc60cfb
Signed-off-by: Anton Johansson <anjo@rev.ng> Message-ID: <20251027-feature-single-binary-hw-v1-v2-1-44478d589ae9@rev.ng> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> [PMD: Do not update riscv_load_kernel()] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
80 lines
3.2 KiB
C
80 lines
3.2 KiB
C
/*
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* QEMU RISC-V Boot Helper
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*
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* Copyright (c) 2017 SiFive, Inc.
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* Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef RISCV_BOOT_H
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#define RISCV_BOOT_H
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#include "exec/cpu-defs.h"
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#include "hw/loader.h"
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#include "hw/riscv/riscv_hart.h"
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#define RISCV32_BIOS_BIN "opensbi-riscv32-generic-fw_dynamic.bin"
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#define RISCV64_BIOS_BIN "opensbi-riscv64-generic-fw_dynamic.bin"
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typedef struct RISCVBootInfo {
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ssize_t kernel_size;
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hwaddr image_low_addr;
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hwaddr image_high_addr;
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hwaddr initrd_start;
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ssize_t initrd_size;
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bool is_32bit;
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} RISCVBootInfo;
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bool riscv_is_32bit(RISCVHartArrayState *harts);
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char *riscv_plic_hart_config_string(int hart_count);
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void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts);
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hwaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info,
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hwaddr firmware_end_addr);
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hwaddr riscv_find_and_load_firmware(MachineState *machine,
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const char *default_machine_firmware,
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hwaddr *firmware_load_addr,
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symbol_fn_t sym_cb);
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const char *riscv_default_firmware_name(RISCVHartArrayState *harts);
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char *riscv_find_firmware(const char *firmware_filename,
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const char *default_machine_firmware);
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hwaddr riscv_load_firmware(const char *firmware_filename,
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hwaddr *firmware_load_addr,
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symbol_fn_t sym_cb);
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void riscv_load_kernel(MachineState *machine,
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RISCVBootInfo *info,
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target_ulong kernel_start_addr,
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bool load_initrd,
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symbol_fn_t sym_cb);
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uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
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MachineState *ms, RISCVBootInfo *info);
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void riscv_load_fdt(hwaddr fdt_addr, void *fdt);
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void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
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hwaddr saddr,
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hwaddr rom_base, hwaddr rom_size,
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uint64_t kernel_entry,
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uint64_t fdt_load_addr);
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void riscv_rom_copy_firmware_info(MachineState *machine,
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RISCVHartArrayState *harts,
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hwaddr rom_base,
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hwaddr rom_size,
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uint32_t reset_vec_size,
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uint64_t kernel_entry);
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void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr);
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void riscv_setup_firmware_boot(MachineState *machine);
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#endif /* RISCV_BOOT_H */
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