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include/semihosting/common-semi: extract common_semi API

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We transform target/{arm,riscv}/common-semi-target.h headers to proper
compilation units, and use them in arm-compat-semi.c.

This way, we can include only the declaration header (which is target
agnostic), and selectively link the appropriate implementation based on
current target.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20250822150058.18692-8-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-ID: <20250922093711.2768983-11-alex.bennee@linaro.org>
This commit is contained in:
Pierrick Bouvier 2025-09-22 10:36:55 +01:00 • committed by Alex Bennée
parent 632308c591
commit 9e65902904
6 changed files with 33 additions and 23 deletions
Download patch file Download diff file Expand all files Collapse all files

6
include/semihosting/common-semi.h
View file

@ -35,5 +35,11 @@
#define COMMON_SEMI_H #define COMMON_SEMI_H
void do_common_semihosting(CPUState *cs); void do_common_semihosting(CPUState *cs);
uint64_t common_semi_arg(CPUState *cs, int argno);
void common_semi_set_ret(CPUState *cs, uint64_t ret);
bool is_64bit_semihosting(CPUArchState *env);
bool common_semi_sys_exit_is_extended(CPUState *cs);
uint64_t common_semi_stack_bottom(CPUState *cs);
bool common_semi_has_synccache(CPUArchState *env);
#endif /* COMMON_SEMI_H */ #endif /* COMMON_SEMI_H */

3
semihosting/arm-compat-semi.c
View file

@ -174,8 +174,7 @@ static LayoutInfo common_semi_find_bases(CPUState *cs)
#endif #endif
#include "cpu.h" #include "semihosting/common-semi.h"
#include "common-semi-target.h"
/* /*
* Read the input value from the argument block; fail the semihosting * Read the input value from the argument block; fail the semihosting

20
target/arm/common-semi-target.h → target/arm/common-semi-target.c
View file

@ -7,12 +7,12 @@
* SPDX-License-Identifier: GPL-2.0-or-later * SPDX-License-Identifier: GPL-2.0-or-later
*/ */
#ifndef TARGET_ARM_COMMON_SEMI_TARGET_H #include "qemu/osdep.h"
#define TARGET_ARM_COMMON_SEMI_TARGET_H #include "cpu.h"
#include "semihosting/common-semi.h"
#include "target/arm/cpu-qom.h" #include "target/arm/cpu-qom.h"
static inline uint64_t common_semi_arg(CPUState *cs, int argno) uint64_t common_semi_arg(CPUState *cs, int argno)
{ {
ARMCPU *cpu = ARM_CPU(cs); ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env; CPUARMState *env = &cpu->env;
@ -23,7 +23,7 @@ static inline uint64_t common_semi_arg(CPUState *cs, int argno)
} }
} }
static inline void common_semi_set_ret(CPUState *cs, uint64_t ret) void common_semi_set_ret(CPUState *cs, uint64_t ret)
{ {
ARMCPU *cpu = ARM_CPU(cs); ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env; CPUARMState *env = &cpu->env;
@ -34,27 +34,25 @@ static inline void common_semi_set_ret(CPUState *cs, uint64_t ret)
} }
} }
static inline bool common_semi_sys_exit_is_extended(CPUState *cs) bool common_semi_sys_exit_is_extended(CPUState *cs)
{ {
return is_a64(cpu_env(cs)); return is_a64(cpu_env(cs));
} }
static inline bool is_64bit_semihosting(CPUArchState *env) bool is_64bit_semihosting(CPUArchState *env)
{ {
return is_a64(env); return is_a64(env);
} }
static inline uint64_t common_semi_stack_bottom(CPUState *cs) uint64_t common_semi_stack_bottom(CPUState *cs)
{ {
ARMCPU *cpu = ARM_CPU(cs); ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env; CPUARMState *env = &cpu->env;
return is_a64(env) ? env->xregs[31] : env->regs[13]; return is_a64(env) ? env->xregs[31] : env->regs[13];
} }
static inline bool common_semi_has_synccache(CPUArchState *env) bool common_semi_has_synccache(CPUArchState *env)
{ {
/* Ok for A64, invalid for A32/T32 */ /* Ok for A64, invalid for A32/T32 */
return is_a64(env); return is_a64(env);
} }
#endif

4
target/arm/meson.build
View file

@ -28,12 +28,16 @@ arm_user_ss.add(files(
'vfp_fpscr.c', 'vfp_fpscr.c',
'el2-stubs.c', 'el2-stubs.c',
)) ))
arm_user_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING',
if_true: files('common-semi-target.c'))
arm_common_system_ss.add(files('cpu.c')) arm_common_system_ss.add(files('cpu.c'))
arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files( arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files(
'cpu32-stubs.c')) 'cpu32-stubs.c'))
arm_common_system_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) arm_common_system_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c'))
arm_common_system_ss.add(when: 'CONFIG_HVF', if_false: files('hvf-stub.c')) arm_common_system_ss.add(when: 'CONFIG_HVF', if_false: files('hvf-stub.c'))
arm_common_system_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING',
if_true: files('common-semi-target.c'))
arm_common_system_ss.add(files( arm_common_system_ss.add(files(
'arch_dump.c', 'arch_dump.c',
'arm-powerctl.c', 'arm-powerctl.c',

19
target/riscv/common-semi-target.h → target/riscv/common-semi-target.c
View file

@ -8,43 +8,42 @@
* SPDX-License-Identifier: GPL-2.0-or-later * SPDX-License-Identifier: GPL-2.0-or-later
*/ */
#ifndef TARGET_RISCV_COMMON_SEMI_TARGET_H #include "qemu/osdep.h"
#define TARGET_RISCV_COMMON_SEMI_TARGET_H #include "cpu.h"
#include "semihosting/common-semi.h"
static inline uint64_t common_semi_arg(CPUState *cs, int argno) uint64_t common_semi_arg(CPUState *cs, int argno)
{ {
RISCVCPU *cpu = RISCV_CPU(cs); RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env; CPURISCVState *env = &cpu->env;
return env->gpr[xA0 + argno]; return env->gpr[xA0 + argno];
} }
static inline void common_semi_set_ret(CPUState *cs, uint64_t ret) void common_semi_set_ret(CPUState *cs, uint64_t ret)
{ {
RISCVCPU *cpu = RISCV_CPU(cs); RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env; CPURISCVState *env = &cpu->env;
env->gpr[xA0] = ret; env->gpr[xA0] = ret;
} }
static inline bool is_64bit_semihosting(CPUArchState *env) bool is_64bit_semihosting(CPUArchState *env)
{ {
return riscv_cpu_mxl(env) != MXL_RV32; return riscv_cpu_mxl(env) != MXL_RV32;
} }
static inline bool common_semi_sys_exit_is_extended(CPUState *cs) bool common_semi_sys_exit_is_extended(CPUState *cs)
{ {
return is_64bit_semihosting(cpu_env(cs)); return is_64bit_semihosting(cpu_env(cs));
} }
static inline uint64_t common_semi_stack_bottom(CPUState *cs) uint64_t common_semi_stack_bottom(CPUState *cs)
{ {
RISCVCPU *cpu = RISCV_CPU(cs); RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env; CPURISCVState *env = &cpu->env;
return env->gpr[xSP]; return env->gpr[xSP];
} }
static inline bool common_semi_has_synccache(CPUArchState *env) bool common_semi_has_synccache(CPUArchState *env)
{ {
return true; return true;
} }
#endif

4
target/riscv/meson.build
View file

@ -8,6 +8,10 @@ gen = [
riscv_ss = ss.source_set() riscv_ss = ss.source_set()
riscv_ss.add(gen) riscv_ss.add(gen)
riscv_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING',
if_true: files('common-semi-target.c'))
riscv_ss.add(files( riscv_ss.add(files(
'cpu.c', 'cpu.c',
'cpu_helper.c', 'cpu_helper.c',