Commit graph

40223 commits

Author SHA1 Message Date
Arun Menon
986c3292c6 migration: Fix regression of passing error_fatal into vmstate_load_state()
error_fatal is passed to vmstate_load_state() and vmstate_save_state()
functions. This was introduced in commit c632ffbd74. This would exit(1)
on error, and therefore does not allow to propagate the error back to
the caller.

To maintain consistency with prior error handling i.e. either propagating
the error to the caller or reporting it, we must set the error within a
local Error object instead of using error_fatal.

Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Signed-off-by: Arun Menon <armenon@redhat.com>
Reviewed-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Link: https://lore.kernel.org/r/20251028-solve_error_fatal_regression-v2-1-dab24c808a28@redhat.com
[peterx: always uninit var ret, per Akihiko]
[peterx: touchups on line ordering, spacings etc.]
Signed-off-by: Peter Xu <peterx@redhat.com>
2025-11-03 16:04:10 -05:00
Bernhard Beschow
74bc6caea9 hw/arm/imx8mp-evk: Fix guest time in KVM mode
The imx8mp DTB hardcodes the clock frequency of the system counter to 8MHz.
In KVM mode, the host CPU is used whose system counter runs at a different
frequency, resulting in the guest clock running slower or faster. Fix this
by not hardcoding the clock frequency which makes the Linux driver read
the real clock frequency from the register.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-id: 20251101120130.236721-3-shentey@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-11-03 10:48:17 +00:00
Bernhard Beschow
094fd7d36f hw/arm/imx8mp-evk: Add KVM support
Allows the imx8mp-evk machine to run guests with KVM acceleration.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-id: 20251101120130.236721-2-shentey@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-11-03 10:47:22 +00:00
Philippe Mathieu-Daudé
0281105bc4 hw/s390x: Use memory_region_size()
MemoryRegion::size is private data of MemoryRegion,
use the proper memory_region_size() getter to get it.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20251028181300.41475-10-philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-11-03 08:27:59 +01:00
Richard Henderson
53b41bb789 target-arm queue:
*  hw/gpio/pl061: Declare pullups/pulldowns as 8-bit types
  * docs/system/arm/virt: Document user-creatable SMMUv3
  * docs/system/security: Restrict "virtualization use case" to specific machines
  * target/arm: Add assert to arm_to_core_mmu_idx()
  * hw/arm/virt: remove deprecated virt-4.1 and virt-4.2 machine types
  * hvf: Refactorings and cleanups
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Merge tag 'pull-target-arm-20251031' of https://gitlab.com/pm215/qemu into staging

target-arm queue:
 *  hw/gpio/pl061: Declare pullups/pulldowns as 8-bit types
 * docs/system/arm/virt: Document user-creatable SMMUv3
 * docs/system/security: Restrict "virtualization use case" to specific machines
 * target/arm: Add assert to arm_to_core_mmu_idx()
 * hw/arm/virt: remove deprecated virt-4.1 and virt-4.2 machine types
 * hvf: Refactorings and cleanups

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# gpg: Signature made Fri 31 Oct 2025 07:32:07 PM CET
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [unknown]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [unknown]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [unknown]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20251031' of https://gitlab.com/pm215/qemu: (38 commits)
  accel/hvf: Trace prefetch abort
  target/arm/hvf/hvf: Document $pc adjustment in HVF & SMC
  target/arm: Share ARM_PSCI_CALL trace event between TCG and HVF
  target/arm: Re-use arm_is_psci_call() in HVF
  target/arm/hvf: Rename 'vgic' -> 'emu_reginfo' in trace events
  target/arm: Rename init_cpreg_list() -> arm_init_cpreg_list()
  accel/hvf: Restrict ARM specific fields of AccelCPUState
  target/arm: Call aarch64_add_pauth_properties() once in host_initfn()
  accel/hvf: Guard hv_vcpu_run() between cpu_exec_start/end() calls
  cpus: Trace cpu_exec_start() and cpu_exec_end() calls
  target/arm/hvf: Keep calling hv_vcpu_run() in loop
  target/arm/hvf: Factor hvf_handle_vmexit() out
  target/i386/hvf: Factor hvf_handle_vmexit() out
  target/arm/hvf: Factor hvf_handle_exception() out
  target/arm/hvf: switch hvf_arm_get_host_cpu_features to not create a vCPU
  target/arm/hvf: Simplify hvf_arm_get_host_cpu_features()
  target/arm/hvf: Hardcode Apple MIDR
  accel/hvf: Implement hvf_arch_vcpu_destroy()
  target/arm/hvf: Mention hvf_inject_interrupts() must run on vCPU thread
  accel/hvf: Mention hvf_arch_update_guest_debug() must run on vCPU
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-11-01 10:52:48 +01:00
Richard Henderson
c5d60e5903 Audio clean-ups
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Merge tag 'audio-test-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging

Audio clean-ups

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# gpg: Signature made Fri 31 Oct 2025 07:43:56 AM CET
# gpg:                using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5
# gpg:                issuer "marcandre.lureau@redhat.com"
# gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" [unknown]
# gpg:                 aka "Marc-André Lureau <marcandre.lureau@gmail.com>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 87A9 BD93 3F87 C606 D276  F62D DAE8 E109 7596 9CE5

* tag 'audio-test-pull-request' of https://gitlab.com/marcandre.lureau/qemu: (36 commits)
  audio: deprecate HMP audio commands
  audio: Rename @endianness argument as @big_endian for clarity
  audio: Remove pointless local variables
  audio: drop needless audio_driver "descr" field
  audio: move capture API to own header
  audio: cleanup, use bool for booleans
  audio: remove dependency on spice header
  audio: move audio.h under include/qemu/
  audio/dbus: use a helper function to set the backend dbus server
  audio: remove QEMUSoundCard
  audio: rename AudioState -> AudioBackend
  audio: move internal APIs to audio_int.h
  audio/replay: fix type punning
  audio: introduce AUD_set_volume_{in,out}_lr()
  audio: remove AUDIO_HOST_ENDIANNESS
  audio: remove some needless headers
  audio: initialize card_head during object init
  audio: register and unregister vmstate with AudioState
  audio: keep vmstate handle with AudioState
  audio: drop needless error message
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-11-01 10:51:32 +01:00
Richard Henderson
0ea4120e39 ppc queue for 10.2
* Firmware updates for SLOF, sam460ex u-boot
 * Removal of unusable e200 CPUs
 * Coverity fixes for fadump
 * Other minor fixes, cleanups for pegasos, spapr.
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Merge tag 'pull-ppc-for-10.2-d4-20251030' of https://gitlab.com/harshpb/qemu into staging

ppc queue for 10.2

* Firmware updates for SLOF, sam460ex u-boot
* Removal of unusable e200 CPUs
* Coverity fixes for fadump
* Other minor fixes, cleanups for pegasos, spapr.

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# gpg: Signature made Thu 30 Oct 2025 09:18:11 AM CET
# gpg:                using RSA key 6B810CD6D2BE10F3883D21424544E994F9D68FBB
# gpg: Good signature from "Harsh Prateek Bora <harsh.prateek.bora@gmail.com>" [undefined]
# gpg:                 aka "Harsh Prateek Bora <harshpb@linux.ibm.com>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6B81 0CD6 D2BE 10F3 883D  2142 4544 E994 F9D6 8FBB

* tag 'pull-ppc-for-10.2-d4-20251030' of https://gitlab.com/harshpb/qemu:
  hw/ppc/pegasos: Update documentation for pegasos1
  hw/ppc/pegasos2: Rename to pegasos
  hw/ppc/pegasos2: Add /chosen/stdin node with VOF
  hw/ppc: Fix memory leak in get_cpu_state_data()
  hw/ppc: Fix missing return on allocation failure
  ppc/spapr: Cleanup MSI IRQ number handling
  target/ppc: Remove the unusable e200 CPUs
  target/ppc/cpu_init: Simplify the setup of the TLBxCFG SPR registers
  hw/ppc/sam460ex: Update u-boot-sam460ex
  pseries: Update SLOF firmware image to release 20251027

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-11-01 09:39:10 +01:00
Philippe Mathieu-Daudé
725770c2cb hw/arm/virt: Remove VirtMachineClass::kvm_no_adjvtime field
The VirtMachineClass::kvm_no_adjvtime field was only used by the
virt-4.2 machine, which got removed. Remove it as now unused, but
keep the ARMCPU homonym property.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20251020094022.68768-5-philmd@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-31 16:26:45 +00:00
Philippe Mathieu-Daudé
c43313a0c7 hw/arm/virt: Remove deprecated virt-4.2 machine
This machine has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6f "docs: document special exception for machine type
deprecation & removal") it can now be removed.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20251020094022.68768-4-philmd@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-31 16:26:45 +00:00
Philippe Mathieu-Daudé
5eb33245f9 hw/arm/virt: Remove VirtMachineClass::no_ged field
The VirtMachineClass::no_ged field was only used by virt-4.1
machine, which got removed. Remove it as now unused.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20251020094022.68768-3-philmd@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-31 16:26:45 +00:00
Philippe Mathieu-Daudé
b7c52f28bf hw/arm/virt: Remove deprecated virt-4.1 machine
This machine has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6f "docs: document special exception for machine type
deprecation & removal") it can now be removed.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20251020094022.68768-2-philmd@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-31 16:26:45 +00:00
Philippe Mathieu-Daudé
92122685e5 hw/gpio/pl061: Declare pullups/pulldowns as 8-bit types
uint8_t is good enough to hold a property "between 0 and 0xff".

Define pullups/pulldowns properties using DEFINE_PROP_UINT8()
macro, remove unnecessary range checks in pl061_realize().
Update the two caller sites.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-31 16:26:44 +00:00
Richard Henderson
c494afbb7d nvme queue
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Merge tag 'pull-nvme-20251030' of https://gitlab.com/birkelund/qemu into staging

nvme queue

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# gpg: Signature made Thu 30 Oct 2025 08:28:56 AM CET
# gpg:                using RSA key 522833AA75E2DCE6A24766C04DE1AF316D4F0DE9
# gpg: Good signature from "Klaus Jensen <its@irrelevant.dk>" [unknown]
# gpg:                 aka "Klaus Jensen <k.jensen@samsung.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: DDCA 4D9C 9EF9 31CC 3468  4272 63D5 6FC5 E55D A838
#      Subkey fingerprint: 5228 33AA 75E2 DCE6 A247  66C0 4DE1 AF31 6D4F 0DE9

* tag 'pull-nvme-20251030' of https://gitlab.com/birkelund/qemu:
  hw/nvme: add atomic boundary support
  hw/nvme: enable ns atomic writes
  hw/nvme: connect SPDM over NVMe Security Send/Recv
  spdm: define SPDM transport enum types
  hw/nvme: add NVMe Admin Security SPDM support
  spdm: add spdm storage transport virtual header
  spdm-socket: add seperate send/recv functions

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-10-31 12:56:05 +01:00
Richard Henderson
3728de3192 Various patches related to single binary work:
- Make hw/arm/ common by adding a QOM type to machines to
   tag in which binary (32 or 64-bit) they can be used.
   Convert the Virt and SBSA-Ref machines.
 - Build Xen files once
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Merge tag 'single-binary-20251030' of https://github.com/philmd/qemu into staging

Various patches related to single binary work:

- Make hw/arm/ common by adding a QOM type to machines to
  tag in which binary (32 or 64-bit) they can be used.
  Convert the Virt and SBSA-Ref machines.
- Build Xen files once

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# gpg: Signature made Thu 30 Oct 2025 02:50:38 PM CET
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'single-binary-20251030' of https://github.com/philmd/qemu: (23 commits)
  hw/riscv: Replace target_ulong uses
  hw/xen: Build only once
  hw/xen: Replace target_ulong by agnostic target_long_bits()
  hw/xen: Use BITS_PER_BYTE & MAKE_64BIT_MASK() in req_size_bits()
  hw/arm/meson: Move Xen files to arm_common_ss[]
  hw/arm/virt: Build only once
  hw/arm/virt-acpi-build: Build only once
  hw/arm/virt-acpi-build: Include missing 'cpu.h' header
  hw/arm/sbsa-ref: Build only once
  hw/arm/sbsa-ref: Include missing 'cpu.h' header
  hw/arm/virt: Get default CPU type at runtime
  hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64()
  qemu/target_info: Add target_base_arm() helper
  qemu/target_info: Add target_aarch64() helper
  qemu/target_info: Add target_arm() helper
  hw/arm/virt: Check accelerator availability at runtime
  hw/arm/virt: Register valid CPU types dynamically
  config/target: Implement per-binary TargetInfo structure (ARM, AARCH64)
  meson: Prepare to accept per-binary TargetInfo structure implementation
  hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-10-31 10:26:34 +01:00
Marc-André Lureau
1e4ebc895a audio: move audio.h under include/qemu/
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
2025-10-30 22:56:51 +04:00
Marc-André Lureau
9628ad8a6e audio: remove QEMUSoundCard
There is no clear need for this extra intermediary structure between
the audio backend and its user.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-10-30 22:56:28 +04:00
Marc-André Lureau
7d75c12ad1 audio: rename AudioState -> AudioBackend
Naming is hard. But in general in QEMU, a host "backend" is the term
used to fullfill the request made by the device or frontend.

AudioBackend will become an abstract base class in a follow-up series.

Currently the frontend is QEMUSoundCard, we are going to drop that next.

Note that "audiodev" is the corresponding QAPI type name (or configuration).

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-10-30 22:56:28 +04:00
Marc-André Lureau
d2b15ae407 audio: introduce AUD_set_volume_{in,out}_lr()
There are 2 sets of functions since the introduction of multi-channel
Volume structure: AUD_set_volume_{in,out} and audio_set_volume_{in,out}.

Use the AUD_ prefix for consistency with other audio.c functions. Rename
the stereo function with "_lr" suffix.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-10-30 22:56:28 +04:00
Marc-André Lureau
eaeafe3074 audio: remove AUDIO_HOST_ENDIANNESS
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-10-30 22:56:28 +04:00
Anton Johansson
dfbf777540 hw/riscv: Replace target_ulong uses
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20251027-feature-single-binary-hw-v1-v2-2-44478d589ae9@rev.ng>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-10-30 14:48:26 +01:00
Philippe Mathieu-Daudé
ad9e070998 hw/xen: Build only once
Now than hw/xen/ files don't use any target-specific code,
we can build all file units once, removing the need for the
xen_specific_ss[] source set.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Message-Id: <20251022140114.72372-4-philmd@linaro.org>
2025-10-30 14:48:26 +01:00
Philippe Mathieu-Daudé
6e63a00522 hw/xen: Replace target_ulong by agnostic target_long_bits()
Both are equivalent:

  target_long_bits()

  sizeof(target_u?long) * BITS_PER_BYTE

Prefer the former which is target-agnostic.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Message-Id: <20251022140114.72372-3-philmd@linaro.org>
2025-10-30 14:48:26 +01:00
Philippe Mathieu-Daudé
a1393a76ce hw/xen: Use BITS_PER_BYTE & MAKE_64BIT_MASK() in req_size_bits()
Replace magic 8 by BITS_PER_BYTE, use MAKE_64BIT_MASK()
instead of open coding it.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Message-Id: <20251022140114.72372-2-philmd@linaro.org>
2025-10-30 14:48:26 +01:00
Philippe Mathieu-Daudé
8299515d64 hw/arm/meson: Move Xen files to arm_common_ss[]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Acked-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20251021210655.59278-1-philmd@linaro.org>
2025-10-30 14:48:26 +01:00
Philippe Mathieu-Daudé
5ec0236f63 hw/arm/virt: Build only once
Previous commits removed the TARGET_AARCH64 uses in virt.c,
we can now move it to arm_common_ss[] and build it once.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Acked-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20251021210934.60483-1-philmd@linaro.org>
2025-10-30 14:48:26 +01:00
Philippe Mathieu-Daudé
2b12ce6d39 hw/arm/virt-acpi-build: Build only once
Previous commits removed the target-specificities,
we can now move virt-acpi-build.c to arm_common_ss[].

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Acked-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20251021210144.58108-9-philmd@linaro.org>
2025-10-30 14:48:26 +01:00
Philippe Mathieu-Daudé
fdda97b47e hw/arm/virt-acpi-build: Include missing 'cpu.h' header
"cpu.h" is indirectly pulled in by another header. Include
it explicitly in order to avoid when changing default CPPFLAGS path:

  hw/arm/virt-acpi-build.c:903:34: error: call to undeclared function 'arm_feature';
    903 |         uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
        |                                  ^
  hw/arm/virt-acpi-build.c:903:53: error: incomplete definition of type 'ARMCPU' (aka 'struct ArchCPU')
    903 |         uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
        |                                               ~~~~~~^
  include/qemu/typedefs.h:30:16: note: forward declaration of 'struct ArchCPU'
     30 | typedef struct ArchCPU ArchCPU;
        |                ^
  hw/arm/virt-acpi-build.c:903:60: error: use of undeclared identifier 'ARM_FEATURE_PMU'
    903 |         uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
        |                                                            ^
  hw/arm/virt-acpi-build.c:993:10: error: use of undeclared identifier 'QEMU_PSCI_CONDUIT_DISABLED'
    993 |     case QEMU_PSCI_CONDUIT_DISABLED:
        |          ^
  hw/arm/virt-acpi-build.c:996:10: error: use of undeclared identifier 'QEMU_PSCI_CONDUIT_HVC'
    996 |     case QEMU_PSCI_CONDUIT_HVC:
        |          ^
  hw/arm/virt-acpi-build.c:1000:10: error: use of undeclared identifier 'QEMU_PSCI_CONDUIT_SMC'
   1000 |     case QEMU_PSCI_CONDUIT_SMC:
        |          ^

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Acked-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20251021210144.58108-8-philmd@linaro.org>
2025-10-30 14:48:26 +01:00
Philippe Mathieu-Daudé
3b958ed662 hw/arm/sbsa-ref: Build only once
Since previous commit allowed the use of accelerator definitions
in common code, we can now move sbsa-ref.c to arm_common_ss[].

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Acked-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20251021210144.58108-7-philmd@linaro.org>
2025-10-30 14:48:26 +01:00
Philippe Mathieu-Daudé
67b2ba55ad hw/arm/sbsa-ref: Include missing 'cpu.h' header
"cpu.h" is indirectly pulled in by another header. Include
it explicitly in order to avoid when changing default CPPFLAGS path:

  hw/arm/sbsa-ref.c:162:25: error: use of undeclared identifier 'ARM_DEFAULT_CPUS_PER_CLUSTER'
    162 |     uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
        |                         ^
  hw/arm/sbsa-ref.c:163:12: error: call to undeclared function 'arm_build_mp_affinity'
    163 |     return arm_build_mp_affinity(idx, clustersz);
        |            ^
  hw/arm/sbsa-ref.c:746:25: error: use of undeclared identifier 'QEMU_PSCI_CONDUIT_DISABLED'
    746 |     sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
        |                         ^

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Acked-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20251021210144.58108-6-philmd@linaro.org>
2025-10-30 14:48:26 +01:00
Philippe Mathieu-Daudé
e22ad85abd hw/arm/virt: Get default CPU type at runtime
Prefer MachineClass::get_default_cpu_type() over
MachineClass::default_cpu_type to get CPU type,
evaluating TCG availability at runtime calling
tcg_enabled().

It's worth noting that this is a behavior change:

- Previously only

  ./configure --disable-tcg --enable-kvm
  ./qemu-system-aarch64 -M virt -accel kvm

  would default to 'max' and

  ./configure --enable-tcg --enable-kvm
  ./qemu-system-aarch64 -M virt -accel kvm

  would default to 'cortex-a15'.

- Afterward, -accel kvm will always default to 'max'.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Zhang Chen <zhangckid@gmail.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Acked-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20251021210144.58108-5-philmd@linaro.org>
2025-10-30 14:48:26 +01:00
Philippe Mathieu-Daudé
ebb643764b hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64()
Replace the target-specific TARGET_AARCH64 definition
by a call to the generic target_aarch64() helper.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Acked-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20251021210144.58108-4-philmd@linaro.org>
2025-10-30 14:48:26 +01:00
Philippe Mathieu-Daudé
9f5791334e hw/arm/virt: Check accelerator availability at runtime
It is not possible to call accelerator runtime helpers
when QOM types are registered, because they depend on
the parsing of the '-accel FOO' command line option,
which happens after main().

Now than get_valid_cpu_types() is called after
accelerator initializations, it is safe to call the
accelerator helpers:

  main
   + configure_accelerators
   + qmp_x_exit_preconfig
     + qemu_init_board
       + machine_run_board_init
         + is_cpu_type_supported

Replace compile-time check on CONFIG_{ACCEL} by
runtime check on {accel}_enabled() helpers.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Acked-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20251021210840.60112-1-philmd@linaro.org>
2025-10-30 14:48:26 +01:00
Philippe Mathieu-Daudé
d4e3377c74 hw/arm/virt: Register valid CPU types dynamically
Replace the static array returned as MachineClass::valid_cpu_types[]
by a runtime one generated by MachineClass::get_valid_cpu_types()
once the machine is created (its options being processed).

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Acked-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20251021211135.61179-1-philmd@linaro.org>
2025-10-30 14:48:26 +01:00
Philippe Mathieu-Daudé
38c5ab4003 hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries
Register machines to be able to run with the qemu-system-arm
and qemu-system-aarch64 binaries, except few machines which
are only available on the qemu-system-aarch64 binary:

  $ git grep TARGET_AARCH64 hw/arm/meson.build
  hw/arm/meson.build:31:arm_common_ss.add(when: ['CONFIG_RASPI', 'TARGET_AARCH64'], if_true: files('bcm2838.c', 'raspi4b.c'))
  hw/arm/meson.build:50:arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files('aspeed_ast27x0.c'))

  $ git grep -W AARCH64 hw/arm/Kconfig
  hw/arm/Kconfig=185=config SBSA_REF
  hw/arm/Kconfig-186-    bool
  hw/arm/Kconfig-187-    default y
  hw/arm/Kconfig:188:    depends on TCG && AARCH64
  --
  hw/arm/Kconfig=413=config XLNX_ZYNQMP_ARM
  hw/arm/Kconfig-414-    bool
  hw/arm/Kconfig-415-    default y if PIXMAN
  hw/arm/Kconfig:416:    depends on TCG && AARCH64
  --
  hw/arm/Kconfig=435=config XLNX_VERSAL
  hw/arm/Kconfig-436-    bool
  hw/arm/Kconfig-437-    default y
  hw/arm/Kconfig:438:    depends on TCG && AARCH64
  --
  hw/arm/Kconfig=475=config NPCM8XX
  hw/arm/Kconfig-476-    bool
  hw/arm/Kconfig-477-    default y
  hw/arm/Kconfig:478:    depends on TCG && AARCH64
  --
  hw/arm/Kconfig=605=config FSL_IMX8MP_EVK
  hw/arm/Kconfig-606-    bool
  hw/arm/Kconfig-607-    default y
  hw/arm/Kconfig:608:    depends on TCG && AARCH64

  $ git grep -wW TARGET_AARCH64 hw/arm | fgrep -4 MACHINE_TYPE_NAME
  ...
  hw/arm/aspeed.c:1939:#ifdef TARGET_AARCH64
  hw/arm/aspeed.c-1940-    }, {
  hw/arm/aspeed.c-1941-        .name          = MACHINE_TYPE_NAME("ast2700a0-evb"),

  hw/arm/aspeed.c-1949-        .name          = MACHINE_TYPE_NAME("ast2700a1-evb"),

  hw/arm/raspi.c:420:#ifdef TARGET_AARCH64
  hw/arm/raspi.c-421-    }, {
  hw/arm/raspi.c-422-        .name           = MACHINE_TYPE_NAME("raspi3ap"),

  hw/arm/raspi.c-429-    }, {
  hw/arm/raspi.c-430-        .name           = MACHINE_TYPE_NAME("raspi3b"),

This can be verified as:

$ diff -u0 <(qemu-system-arm -M help) <(qemu-system-aarch64 -M help)
  @@ -1,0 +2,3 @@
  +xlnx-versal-virt     AMD Versal Virtual development board (alias of amd-versal-virt)
  +amd-versal-virt      AMD Versal Virtual development board
  +amd-versal2-virt     AMD Versal Gen 2 Virtual development board
  @@ -4,0 +8,5 @@
  +ast2700a0-evb        Aspeed AST2700 A0 EVB (Cortex-A35)
  +ast2700-evb          Aspeed AST2700 A1 EVB (Cortex-A35) (alias of ast2700a1-evb)
  +ast2700a1-evb        Aspeed AST2700 A1 EVB (Cortex-A35)
  +ast2700fc            ast2700 full core support (alias of ast2700fc)
  +ast2700fc            ast2700 full core support
  @@ -20,0 +29 @@
  +imx8mp-evk           NXP i.MX 8M Plus EVK Board
  @@ -47,0 +57 @@
  +npcm845-evb          Nuvoton NPCM845 Evaluation Board (Cortex-A35)
  @@ -60,0 +71,3 @@
  +raspi3ap             Raspberry Pi 3A+ (revision 1.0)
  +raspi3b              Raspberry Pi 3B (revision 1.2)
  +raspi4b              Raspberry Pi 4B (revision 1.5)
  @@ -66,0 +80 @@
  +sbsa-ref             QEMU 'SBSA Reference' ARM Virtual Machine
  @@ -99,0 +114 @@
  +xlnx-zcu102          Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5Fs based on the value of smp

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Acked-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20251021205741.57109-5-philmd@linaro.org>
2025-10-30 14:48:24 +01:00
Marc-André Lureau
5fb347dea0 hw/audio: drop audio_model.isa
That's no longer necessary, the code is bus-agnostic.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-10-30 13:30:06 +04:00
Marc-André Lureau
b181226e4e hw/audio: generalize audio_model.init()
It is no longer PCI bus only.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-10-30 13:30:06 +04:00
Marc-André Lureau
96da2b29f4 hw/audio: simplify 'hda' audio init code
For consistency, use only qdev_device_add() to instantiate the devices.
We can't rely on automatic bus lookup for the "hda-duplex" device though
as it may end up on a different "intel-hda" bus...

This allows to make init() callback bus-agnostic next.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-10-30 13:30:06 +04:00
Marc-André Lureau
341eaea215 hw/audio/virtio-snd-pci: remove custom model callback
virtio-snd can rely on the default code to instantiate the device and
set the audiodev.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-10-30 13:30:06 +04:00
Marc-André Lureau
635af57068 hw/audio: use better naming for -audio model handling code
All the functions are about "-audio model=" handling, a simpler
way to setup audio. Rename functions/variables to reflect this better.

audio_register_model_with_cb() dropped "pci" from the name, since it
will be generalized next.

deprecated_register_soundhw() was actually not a function to be
removed since it's used for "-audio model=" aliasing.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-10-30 13:30:06 +04:00
Marc-André Lureau
5c7b8a6d61 hw/audio: look up the default bus from the device class
Generalize and simplify the device model creation.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-10-30 13:30:03 +04:00
Richard Henderson
0979667049 Block layer patches
- Expose block limits in monitor and qemu-img info
 - Resize: Refresh filter node size when its child was resized
 - Support configuring stats-intervals in -device (instead of only -drive)
 - luks: Fix QMP x-blockdev-amend crash and image creation with detached-header
 - iotests: Several test case fixes
 - Code cleanups
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Merge tag 'for-upstream' of https://repo.or.cz/qemu/kevin into staging

Block layer patches

- Expose block limits in monitor and qemu-img info
- Resize: Refresh filter node size when its child was resized
- Support configuring stats-intervals in -device (instead of only -drive)
- luks: Fix QMP x-blockdev-amend crash and image creation with detached-header
- iotests: Several test case fixes
- Code cleanups

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# gpg: Signature made Wed 29 Oct 2025 01:02:10 PM CET
# gpg:                using RSA key DC3DEB159A9AF95D3D7456FE7F09B272C88F2FD6
# gpg:                issuer "kwolf@redhat.com"
# gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: DC3D EB15 9A9A F95D 3D74  56FE 7F09 B272 C88F 2FD6

* tag 'for-upstream' of https://repo.or.cz/qemu/kevin:
  qemu-img info: Add cache mode option
  qemu-img info: Optionally show block limits
  block: Expose block limits for images in QMP
  block: Improve comments in BlockLimits
  iotests: add test for resizing a 'file' node below a 'raw' node
  iotests: add test for resizing a node below filters
  block: implement 'resize' callback for child_of_bds class
  block: make bdrv_co_parent_cb_resize() a proper IO API function
  include/block/block_int-common: document when resize callback is used
  MAINTAINERS: Mark VHDX block driver as "Odd Fixes"
  block: enable stats-intervals for storage devices
  iotests: Adjust fuse-allow-other expected output
  iotests: Adjust nbd expected outputs to match current behavior
  block/curl.c: Fix CURLOPT_VERBOSE parameter type
  block/monitor: Use hmp_handle_error to report error
  block: fix luks 'amend' when run in coroutine
  block: remove 'detached-header' option from opts after use
  tests/qemu-iotests: Mark the 'inactive-node-nbd' as unsupported with -luks

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-10-30 09:24:15 +01:00
BALATON Zoltan
b943bb3ce9
hw/ppc/pegasos2: Rename to pegasos
Now that we also emulate pegasos1 it is not only about pegasos2 so
rename to a more generic name encompassing both.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Link: https://lore.kernel.org/r/275cd2d5074b76b4a504a01f658e85ed7994ea3e.1761346145.git.balaton@eik.bme.hu
Message-ID: <275cd2d5074b76b4a504a01f658e85ed7994ea3e.1761346145.git.balaton@eik.bme.hu>
2025-10-30 13:40:38 +05:30
BALATON Zoltan
bd7bf827bb
hw/ppc/pegasos2: Add /chosen/stdin node with VOF
Some very old Linux kernels fail to start if /chosen/stdin is not
found so add it to the device tree when using VOF.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Link: https://lore.kernel.org/r/642ef77674d08ba466e7a2beb4858ab1e67776ae.1761346145.git.balaton@eik.bme.hu
Message-ID: <642ef77674d08ba466e7a2beb4858ab1e67776ae.1761346145.git.balaton@eik.bme.hu>
2025-10-30 13:40:38 +05:30
Shivang Upadhyay
ec2b08c74d
hw/ppc: Fix memory leak in get_cpu_state_data()
Fixes coverity (CID 1642024)

Cc: Aditya Gupta <adityag@linux.ibm.com>
Cc: Harsh Prateek Bora <harshpb@linux.ibm.com>
Link: https://lore.kernel.org/qemu-devel/CAFEAcA_Bm52bkPi9MH_uugXRR5fj48RtpbOnPNFQtbX=7Mz_yw@mail.gmail.com/
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Shivang Upadhyay <shivangu@linux.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Link: https://lore.kernel.org/r/20251028080551.92722-3-shivangu@linux.ibm.com
Message-ID: <20251028080551.92722-3-shivangu@linux.ibm.com>
2025-10-30 13:37:18 +05:30
Shivang Upadhyay
4a0ebccf92
hw/ppc: Fix missing return on allocation failure
Fixes coverity (CID 1642026)

Cc: Aditya Gupta <adityag@linux.ibm.com>
Cc: Harsh Prateek Bora <harshpb@linux.ibm.com>
Link: https://lore.kernel.org/qemu-devel/CAFEAcA-SPmsnU1wzsWxBcFC=ZM_DDhPEg1N4iX9Q4bL1xOnwBg@mail.gmail.com/
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Shivang Upadhyay <shivangu@linux.ibm.com>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Link: https://lore.kernel.org/r/20251028080551.92722-2-shivangu@linux.ibm.com
Message-ID: <20251028080551.92722-2-shivangu@linux.ibm.com>
2025-10-30 13:37:10 +05:30
Yoges Vyas
552e329910
ppc/spapr: Cleanup MSI IRQ number handling
Now that spapr_irq_nr_msis() returns a constant value,
lets replace it with a macro.
Ref: https://lore.kernel.org/qemu-devel/bf149815-9782-4964-953d-73658b1043c9@linux.ibm.com/

Suggested-by: Chinmay Rath <rathc@linux.ibm.com>
Signed-off-by: Yogesh Vyas <yvyas1991@gmail.com>
Reviewed-by: Chinmay Rath <rathc@linux.ibm.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Link: https://lore.kernel.org/r/20251026074852.53691-1-yvyas1991@gmail.com
Message-ID: <20251026074852.53691-1-yvyas1991@gmail.com>
2025-10-30 12:45:32 +05:30
BALATON Zoltan
2a62bbf4ed
hw/ppc/sam460ex: Update u-boot-sam460ex
Update the sam460ex firmware to match 2015.c version from the machine
vendor which fixes USB devices and some other bugs. Also cherry pick
some commits from upstream U-Boot that moves licenses in a subdir and
allows gitlab to correctly detect and show license information. Drop
version number from the binary name to avoid needing to change it in
case of future updates.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20251028151923.10DBB5972E5@zero.eik.bme.hu>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
2025-10-30 12:33:10 +05:30
Alan Adamson
bce51b8370 hw/nvme: add atomic boundary support
Add support for the namespace atomic boundary paramters: NABO, NABSN, and NABSPF.

Writes that cross an atomic boundary whose size is less than or equal to values
reported by AWUN/AWUPF are guaranteed to be atomic. If AWUN/AWUPF is set to zero,
writes that cross an atomic boundary are not guaranteed to be atomic.

The value reported by NABO field indicates the LBA on this namespace where the
first atomic boundary starts.

New NVMe QEMU Paramters (See NVMe Specification for details):
        atomic.nabo=UINT16 (default: 0)
        atomic.nabsn=UINT16 (default: 0)
        atomic.nabspf=UINT16 (default: 0)

See the NVMe Specification for more information.

Signed-off-by: Alan Adamson <alan.adamson@oracle.com>
Reviewed-by: Jesper Wendel Devantier <foss@defmacro.it>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2025-10-30 07:07:14 +01:00
Alan Adamson
3b41acc962 hw/nvme: enable ns atomic writes
Add support for the namespace atomic paramters: NAWUN and NAWUN. Namespace
Atomic Compare and Write Unit (NACWU) is not currently supported.

Writes that adhere to the NACWU and NAWUPF parameters are guaranteed to be
atomic.

New NVMe QEMU Paramters (See NVMe Specification for details):
        atomic.nawun=UINT16 (default: 0)
        atomic.nawupf=UINT16 (default: 0)
        atomic.nsfeat (default off) - Set Namespace Supported Atomic Boundary &
                Power (NSABP) bit in Namespace Features (NSFEAT) in the Identify
                Namespace Data Structure

See the NVMe Specification for more information.

Signed-off-by: Alan Adamson <alan.adamson@oracle.com>
Reviewed-by: Jesper Wendel Devantier <foss@defmacro.it>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2025-10-30 07:07:14 +01:00
Wilfred Mallawa
7f2eeccb4b hw/nvme: connect SPDM over NVMe Security Send/Recv
This patch extends the existing support we have for NVMe with only DoE
to also add support to SPDM over the NVMe Security Send/Recv commands.

With the new definition of the `spdm-trans` argument, users can specify
`spdm_trans=nvme` or `spdm_trans=doe`. This allows us to select the SPDM
transport respectively. SPDM over the NVMe Security Send/Recv commands
are defined in the DMTF DSP0286.

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
[k.jensen: fix declaration in case statement; fix quotes in docs]
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2025-10-30 07:07:14 +01:00