Uploading the cache from the runner takes a long time in the MSYS2
job, mostly due to the size of the compiler cache.
However, looking at runs with a non-poluted cache, it seems like
you can get a build with a 99% hit rate already with ~ 160 MiB cache
size, so the compiler cache with 500 MiB certainly contains a lot of
stale files. Thus decrease the size of the ccache to a more reasonable
value to speed up the MSYS2 job in our CI.
While at it, also add a "du -sh" for the build folder to get a better
feeling for the amount of object code that is required for the build,
and publish the list of files in /var/cache to be able to better
analyze what is really clogging our cache here.
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20251020161759.50241-1-thuth@redhat.com>
The MachineClass::fixup_ram_size callback, which was added
in commit 5c30ef937f ("vl/s390x: fixup ram sizes for compat
machines"), was only used by the s390-ccw-virtio-4.2 machine,
which got removed. Remove it as now unused.
Reported-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20251020094903.72182-4-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
The SCLPDevice::increment_size field was only used by the
s390-ccw-virtio-4.2 machine, which got removed. Remove it
as now unused, along with the sclp_memory_init() method.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20251020094903.72182-3-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
This machine has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6f "docs: document special exception for machine type
deprecation & removal") it can now be removed.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20251020094903.72182-2-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Add QAPI event SCLP_CPI_INFO_AVAILABLE to notify the availability
of Control-Program Identification data in QOM.
Signed-off-by: Shalini Chellathurai Saroja <shalini@linux.ibm.com>
Suggested-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Hendrik Brueckner <brueckner@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20251016121708.334133-1-shalini@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
The coverity-scan upload job has started failing as of 30th
September:
[ERROR] Cannot find '/usr/bin/file' command, and no 'file' command is found in the PATH
Coverity Capture uses this tool to identify the file type of executables.
Please ensure '/usr/bin/file' is available, or add the 'file' utility to your PATH.
This seems to have broken when we moved our containers from Fedora 40
to 41 -- probably F40 indirectly pulled in 'file' via some other
dependency, but in F41 it does not.
Explicitly install 'file' for the coverity job, in the same way we
already do for curl and wget.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251017133156.926094-1-peter.maydell@linaro.org>
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Merge tag 'pull-tcg-20251019' of https://gitlab.com/rth7680/qemu into staging
tcg: Remove support for 32-bit mips/ppc hosts
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# gpg: Signature made Sun 19 Oct 2025 11:25:25 AM PDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]
* tag 'pull-tcg-20251019' of https://gitlab.com/rth7680/qemu:
tcg/ppc: Remove support for 32-bit hosts
tcg/ppc: Remove dead cases from tcg_target_op_def
buildsys: Remove support for 32-bit PPC hosts
tcg/mips: Remove ALIAS_PADD, ALIAS_PADDI
tcg/mips: Remove support for 32-bit hosts
tcg/mips: Remove support for O32 and N32 ABIs
kvm/mips: Remove support for 32-bit hosts
buildsys: Remove support for 32-bit MIPS hosts
gitlab: Stop cross-testing for 32-bit MIPS hosts
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
32-bit host support is deprecated since commit 6d701c9bac
("meson: Deprecate 32-bit host support"), released as v10.0.
The next release being v10.2, we can remove the TCG backend
for 32-bit PPC hosts.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251014173900.87497-2-philmd@linaro.org>
Missed some lines when converting to TCGOutOpQemuLdSt*.
Fixes: 86fe5c2597 ("tcg: Convert qemu_st{2} to TCGOutOpLdSt{2}")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
indent on macOS, installed via homebrew, doesn't support -linux. Only
run indent on linux hosts.
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
The purpose of the prepare script is to invoke `cpp` to preprocess input
to idef-parser by expanding a few select macros. On macOS `cpp`
expands into `clang ... -traditional-cpp` which breaks macro
concatenation. Replace `cpp` with `${compiler} -E`
and replace the script with a meson custom_target.
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
To remove any confusion with HVX or other potential store instructions,
we'll qualify this context var with "scalar".
Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Cover cs0,1 register corruption in the signal_context test case.
lc0, sa0 registers previously omitted from the clobbers list
are now captured.
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Link: https://lore.kernel.org/qemu-devel/023e01dc389c$faf84320$f0e8c960$@gmail.com/
Suggested-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Change the user_regs_struct to use abi_ulong instead of
target_ulong.
Link: https://lore.kernel.org/qemu-devel/7bf3d8c5-df07-4cbd-ba62-4c7246a5f96b@linaro.org/
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
In order to correspond with the kernel, we've now (1) moved the
preds[] to the right offset and combined the representation as a single
ulong "p3_0", (2), added the cs{0,1} registers, (3) added a pad for 48
words, (4) added the user regs structure to an 8-byte aligned
target_sigcontext structure.
Co-authored-by: Alex Rønne Petersen <alex@alexrp.com>
Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Stop detecting 32-bit PPC host as supported.
See previous commit for rationale.
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
[rth: Retain _ARCH_PPC64 check in udiv_qrnnd]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251014173900.87497-4-philmd@linaro.org>
These aliases existed to simplify code for O32 and N32.
Now that the 64-bit abi is the only one supported, we
can use the DADD* instructions directly.
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
32-bit host support is deprecated since commit 6d701c9bac
("meson: Deprecate 32-bit host support"), released as v10.0.
The next release being v10.2, we can remove the TCG backend
for 32-bit MIPS hosts.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251009195210.33161-6-philmd@linaro.org>
See previous commit for rationale.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251009195210.33161-5-philmd@linaro.org>
See previous commit for rationale.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251009195210.33161-7-philmd@linaro.org>
Stop detecting 32-bit MIPS host as supported, update the
deprecation document. See previous commit for rationale.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251009195210.33161-8-philmd@linaro.org>
32-bit host support is deprecated since commit 6d701c9bac
("meson: Deprecate 32-bit host support"). Next commits will
remove support for 32-bit MIPS hosts. Stop cross-building
QEMU on our CI.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251009195210.33161-3-philmd@linaro.org>
* Clean ups for some minor issues in functional tests
* Don't ignore errors of address_space_rw in s390x MMU code
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Merge tag 'pull-request-2025-10-16' of https://gitlab.com/thuth/qemu into staging
* Improve cache handling for the msys2 CI and the functional asset cache
* Clean ups for some minor issues in functional tests
* Don't ignore errors of address_space_rw in s390x MMU code
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# gpg: Signature made Thu 16 Oct 2025 09:25:16 AM PDT
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [unknown]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [unknown]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* tag 'pull-request-2025-10-16' of https://gitlab.com/thuth/qemu:
target/s390x/mmu_helper: Do not ignore address_space_rw() errors
target/s390x/mmu_helper: Simplify s390_cpu_virt_mem_rw() logic
tests/functional: ensure GDB client is stopped on error
tests/functional: remove use of getLogger in reverse debuging
tests/functional/alpha: Remove superfluous fetch() line from the clipper test
tests: Evict stale files in the functional download cache after a while
tests/functional: Set current time stamp of assets when using them
gitlab: purge msys pacman cache
tests/functional/aarch64: Drop some sbsaref_alpine tests
python/qemu: Replace some remaining "avocados" with "functional tests"
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
If a address_space_rw() call ever fails, break the loop and
return the PGM_ADDRESSING error (after triggering an access
exception).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20251008141410.99865-3-philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
In order to simplify the next commit, move the
trigger_access_exception() call after the address_space_rw()
calls. No logical change intended.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20251008141410.99865-2-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
If the reverse_debugging_run method fails, the GDB client will not
be closed resulting in python complaining about resource leaks.
Hoisting the GDB client creation into the caller allows this to
be cleaned up easily. While doing this, also move the VM shutdown
call to match.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-ID: <20251014140047.385347-3-berrange@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
This fixes the gap left by
commit 8a44d8c2ac
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: Fri Sep 12 19:22:00 2025 +0100
tests/functional: use self.log for all logging
ensuring that log message from the reverse debugging test actually
make it into the logfile on disk.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-ID: <20251014140047.385347-2-berrange@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Tested-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
The kernel asset is retrieved automatically via the uncompress()
line below the fetch(), so the fetch() is simply not necessary here.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20251010144525.842462-1-thuth@redhat.com>
The download cache of the functional tests is currently only growing.
But sometimes tests get removed or changed to use different assets,
thus we should clean up the stale old assets after a while when they
are not in use anymore. So add a script that looks at the time stamps
of the assets and removes them if they haven't been touched for more
than half of a year. Since there might also be some assets around that
have been added to the cache before we added the time stamp files,
assume a default time stamp that is close to the creation date of this
patch, so that we don't delete these files too early (so we still have
all assets around in case we have to bisect an issue in the recent past
of QEMU).
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20251014083424.103202-3-thuth@redhat.com>
We are going to remove obsolete assets from the cache, so keep
the time stamps of the assets that we use up-to-date to have a way
to detect stale assets later.
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20251014083424.103202-2-thuth@redhat.com>
For the Windows msys2 CI job we install many packages using pacman
and use the GitLab cache to preserve the pacman cache across CI
runs. While metadata still needs downloading, this avoids pacman
re-downloading packages from msys2 if they have not changed.
The problem is that pacman never automatically purges anything
from its package cache. Thus the GitLab cache is growing without
bound and packing/unpacking the cache is consuming an increasing
amount of time in the CI job.
If we run 'pacman -Sc' /after/ installing our desired package set,
it will purge any cached downloaded packages that are not matching
any installed package.
This will (currently) cap the pacman download cache at approx
256 MB.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Tested-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-ID: <20251010160545.144760-1-berrange@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
test_sbsaref_alpine is one of the longest running test in our testsuite,
because it does a full Linux boot a couple of times, for various different
CPU configurations. That's quite a lot of testing each time, for a rather
small additional test coverage. Thus let's drop some of the tests that don't
provide much in addition to the other ones.
Suggested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20251006161850.181998-1-thuth@redhat.com>
The avocado tests have been replaced by the new functional tests,
so also update this in the README.rst files in the python directory
accordingly.
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20251008131936.71160-1-thuth@redhat.com>
Do not let git-shortlog make distinction between:
. Clément Mathieu--Drif
. Clement Mathieu--Drif
. CLEMENT MATHIEU--DRIF
as this is the same person.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Message-Id: <20251009070512.8736-3-philmd@linaro.org>
MicroBlaze CPU model has a "little-endian" property, pointing to
the @endi internal field. Commit c36ec3a965 ("hw/microblaze:
Explicit CPU endianness") took care of having all MicroBlaze
boards with an explicit default endianness, so later commit
415aae543e ("target/microblaze: Consider endianness while
translating code") could infer the endianness at runtime from
the @endi field, and not a compile time via the TARGET_BIG_ENDIAN
definition. Doing so, we forgot to make the endianness explicit
on user emulation, so there all CPUs are started with the default
"little-endian=off" value, leading to breaking support for little
endian binaries:
$ readelf -h ./hello-world-mbel
ELF Header:
Magic: 7f 45 4c 46 01 01 01 00 00 00 00 00 00 00 00 00
Class: ELF32
Data: 2's complement, little endian
$ qemu-microblazeel ./hello-world-mbel
qemu: uncaught target signal 11 (Segmentation fault) - core dumped
Segmentation fault (core dumped)
Fix by restoring the previous behavior of starting with the
builtin endianness of the binary:
$ qemu-microblazeel ./hello-world-mbel
Hello World
Cc: qemu-stable@nongnu.org
Fixes: 415aae543e ("target/microblaze: Consider endianness while translating code")
Reported-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Message-Id: <20251006173350.17455-1-philmd@linaro.org>
Since commit bb5de52524 ("target: Widen pc/cs_base in
cpu_get_tb_cpu_state"), cpu_get_tb_cpu_state() expects
a uint64_t type for cs_base.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20251008051529.86378-3-philmd@linaro.org>
Since commit 85c19af63e ("include/exec: Use vaddr in DisasContextBase
for virtual addresses") the DisasContextBase::pc_first field is a
vaddr type.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20251008051529.86378-2-philmd@linaro.org>
Commit b7ecba0f6f ("docs/devel/loads-stores.rst: Document our
various load and store APIs") mentioned cpu_physical_memory_*()
methods are legacy, the replacement being address_space_*().
Replace the *_map() / *_unmap() methods in the SIMCALL helper,
using the vCPU default address space. No behavioral change expected.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20251002145742.75624-6-philmd@linaro.org>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
The TriCore target is only built as 32-bit:
$ git grep TARGET_LONG_BITS configs/targets/tricore-*
configs/targets/tricore-softmmu.mak:2:TARGET_LONG_BITS=32
Replace:
TCGv -> TCGv_i32
tcg_temp_new -> tcg_temp_new_i32
This is a mechanical replacement, adapting style to pass
the checkpatch.pl script.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251010052141.42460-13-philmd@linaro.org>
Rely on the linker to optimize at linking time.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251010052141.42460-12-philmd@linaro.org>
Unify style, always pass DisasContext as the first argument.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251010052141.42460-11-philmd@linaro.org>
The TriCore target is only built as 32-bit:
$ git grep TARGET_LONG_BITS configs/targets/tricore-*
configs/targets/tricore-softmmu.mak:2:TARGET_LONG_BITS=32
Therefore tcg_FOO_tl() always expands to tcg_FOO_i32().
This is a mechanical replacement.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251010052141.42460-10-philmd@linaro.org>
The TriCore target is only built as 32-bit, so tcg_gen_ld32u_tl()
expands to tcg_gen_ld_i32(). Use the latter to simplify the next
commit mechanical change.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251010052141.42460-9-philmd@linaro.org>
CPUTriCoreState register are declared as uint32_t since the
target introduction in commit 48e06fe0ed ("target-tricore:
Add target stubs and qom-cpu").
Mechanical replacement of:
TCGv -> TCGv_i32
tcg_temp_new -> tcg_temp_new_i32
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251010052141.42460-8-philmd@linaro.org>
The TriCore target is only built as 32-bit:
$ git grep TARGET_LONG_BITS configs/targets/tricore-*
configs/targets/tricore-softmmu.mak:2:TARGET_LONG_BITS=32
Therefore target_ulong type always expands to uint32_t.
This is a mechanical replacement.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251010052141.42460-7-philmd@linaro.org>
